公开(公告)号：US10572438B1

公开(公告)日：2020-02-25

申请号：US16295046

申请日：2019-03-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Christopher Kong Yee Chun ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F1/10 ,  H04L12/40 ,  H04L12/403 ,  G06F1/12 ,  G06F1/08

Abstract: Systems, methods, and apparatus for improving end-to-end timing closure of a serial bus are described. An apparatus is coupled to a serial bus through an interface circuit and has a clock generator that provides a first clock signal, a delay circuit that is adapted to generate a second clock signal by delaying the first clock signal, and a controller that is configured to cause the interface circuit to use an edge of the first clock signal to initiate transmission of a first data bit over the serial bus during a write operation, delay the first clock signal to obtain a second clock signal, and cause the interface circuit to use an edge of the second clock signal to capture a second data bit from the serial bus during a read operation. The edge of the second clock signal is delayed with respect to the edge of the first clock signal.

公开(公告)号：US10528503B1

公开(公告)日：2020-01-07

申请号：US16036416

申请日：2018-07-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/00 ,  G06F13/366 ,  G06F13/42 ,  G06F13/16

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

公开(公告)号：US10447464B2

公开(公告)日：2019-10-15

申请号：US16173949

申请日：2018-10-29

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Elisha Ulmer

IPC: H04L12/40 ,  H04L7/033

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a receiving device includes detecting a first transition in a signal received from a receive line of a UART after the receive line has been idle or following transmission of a stop bit on the receive line, detecting a second transition in the signal, synchronizing a sampling clock to the second transition, where clock cycles of the sampling clock are double the duration between the first transition and the second transition, and using the sampling clock to capture a byte of data from the receive line. One clock cycle of the sampling clock may be consumed while receiving each bit of data.

公开(公告)号：US10423551B2

公开(公告)日：2019-09-24

申请号：US15698191

申请日：2017-09-07

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Helena Deirdre O'Shea ,  Richard Dominic Wietfeldt

IPC: G06F13/28 ,  H04W28/06 ,  H04L29/06 ,  G06F13/42

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a device operating as a bus master may include transmitting a first pulse on a first wire of a multi-wire interface, transmitting a second pulse on a second wire of the multi-wire interface while the first pulse is present on the first wire of the multi-wire interface, and initiating a low-latency mode of communication immediately after termination of the first pulse. The second pulse may be shorter in duration than the first pulse.

公开(公告)号：US10417161B2

公开(公告)日：2019-09-17

申请号：US16219698

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'Shea ,  Lalan Jee Mishra ,  Amit Gil ,  Gary Chang ,  Mohit Kishore Prasad ,  Richard Dominic Wietfeldt ,  Vinay Jain

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.

公开(公告)号：US10402365B2

公开(公告)日：2019-09-03

申请号：US16201369

申请日：2018-11-27

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/364 ,  H04L5/00

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in multiple modes that employ additional wires for communicating data such that the bus width may be dynamically extended to improve bandwidth and/or throughput. One method includes transmitting a set of frames or sequences of symbols configured to carry up to a maximum number of data bytes over the serial bus, transmitting control signaling over a first data lane and the clock lane after the set of frames or sequences of symbols has been transmitted, and transmitting a first signal over a second data lane while transmitting the control signaling that may indicate whether the set of frames or sequences of symbols includes padding. The first signal may indicate a number of valid bytes or words in the set of frames or sequences of symbols.

公开(公告)号：US10339089B2

公开(公告)日：2019-07-02

申请号：US14924844

申请日：2015-10-28

Applicant: QUALCOMM Incorporated

Inventor： Nir Gerber ,  Itamar Berman ,  Yair Cassuto ,  Lalan Jee Mishra

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

Abstract: Enhanced communications over a Universal Serial Bus (USB) Type-C cable are disclosed. In one aspect, a link control circuit is provided in a USB host to enable one or more communication circuits in the USB host to transmit and receive protocol-specific data over a sideband use (SBU) interface according to communication protocols that may or may not be USB compliant. In another aspect, the link control circuit is provided in a USB client to enable one or more communication circuits in the USB client to transmit and receive protocol-specific data over the SBU interface according to communication protocols that may or may not be USB compliant. By configuring the USB host and the USB client to support multi-protocol communications via the SBU interface, it is possible to enable more flexible architectural design in mobile communication devices for enhanced performance and reduced costs.

公开(公告)号：US10289579B2

公开(公告)日：2019-05-14

申请号：US14965511

申请日：2015-12-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Peter Shah

IPC: G06F13/24 ,  G06F13/10 ,  H03M1/78

Abstract: A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

公开(公告)号：US10140242B2

公开(公告)日：2018-11-27

申请号：US15242368

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

IPC: G06F13/20 ,  G06F13/42 ,  G06F15/177 ,  G06F15/17 ,  G06F13/40 ,  G05B19/05 ,  G06F13/38

Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

公开(公告)号：US20180241816A1

公开(公告)日：2018-08-23

申请号：US15956708

申请日：2018-04-18

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  James Panian ,  Richard Wietfeldt

IPC: H04L29/08 ,  H04L29/12 ,  G06F13/42

CPC classification number: H04L67/1091 ,  G06F13/4247 ,  G06F2213/0052 ,  H04L61/2007 ,  H04L61/604

Abstract: An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through P2P links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. The host device receives a unique concatenated address from each slave device that represents a concatenation of the node ID for the slave and the node ID for any intervening interfaces between the slave device and the host device. The host device then assigns a unique Cartesian address to each slave device.