公开(公告)号：US20200168288A1

公开(公告)日：2020-05-28

申请号：US16690743

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G11C29/50 ,  G06F11/10

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20200026677A1

公开(公告)日：2020-01-23

申请号：US16525315

申请日：2019-07-29

Applicant: Rambus Inc.

Inventor： Amir Amirkhany ,  Suresh Rajan ,  Ravindranath Kollipara ,  Ian Shaeffer ,  David A. Secker

IPC: G06F13/40 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

公开(公告)号：US10223299B2

公开(公告)日：2019-03-05

申请号：US15101870

申请日：2014-12-18

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Abhijit Abhyankar ,  Suresh Rajan

IPC: G06F13/16 ,  G06F11/20 ,  G06F13/00 ,  G06F13/42

Abstract: A memory controller and buffers on memory modules each operate in two modes, depending on the type of mother-board through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.

公开(公告)号：US10198314B2

公开(公告)日：2019-02-05

申请号：US14285467

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Brent Haukness ,  Scott C. Best ,  Wayne F. Ellis

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C11/40 ,  G11C29/04

Abstract: A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word.

公开(公告)号：US20180285013A1

公开(公告)日：2018-10-04

申请号：US15745396

申请日：2016-07-14

Applicant: Rambus Inc.

Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

IPC: G06F3/06 ,  G06F13/16

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

公开(公告)号：US09826638B2

公开(公告)日：2017-11-21

申请号：US14515380

申请日：2014-10-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: G11C5/06 ,  H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G11C5/04 ,  G11C7/10

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

公开(公告)号：US09691504B2

公开(公告)日：2017-06-27

申请号：US14353401

申请日：2012-10-19

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/00 ,  G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20160189764A1

公开(公告)日：2016-06-30

申请号：US14869294

申请日：2015-09-29

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US09232651B2

公开(公告)日：2016-01-05

申请号：US14687687

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11 ,  G11C11/4093 ,  H05K1/18 ,  G06F15/78 ,  G11C11/408 ,  G06F13/16 ,  G06F13/40 ,  G06F1/18 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H01R3/00 ,  H03M9/00

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.

Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 主板基板的一个实现包括第一和第二组数据线，布置成第一组半字节的第一组数据线和第二组数据线被布置成第二组半字节，其中第一和第 第二组半字节包括用于相应定时信号的相应定时线。 主板基板还包括连接到第一组数据线的处理器插座，经由第一组半字节的第一子集连接到处理器插座的第一插槽，以及经由第二组子集 第一组半字节，并通过第二组半字节连接到第一个插槽。

公开(公告)号：US20150223333A1

公开(公告)日：2015-08-06

申请号：US14687687

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan

IPC: H05K1/11

CPC classification number: H05K1/11 ,  G06F1/184 ,  G06F13/1694 ,  G06F13/4068 ,  G06F15/7803 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C11/4082 ,  G11C11/4093 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a motherboard substrate includes first and second sets of data lines, the first set of data lines arranged into a first set of nibbles and the second set of data lines are arranged into a second set of nibbles with each of the first and the second sets of nibbles including a respective timing line for a respective timing signal. The motherboard substrate also includes a processor socket connected to the first set of data lines, a first slot connected to the processor socket via a first subset of the first set of nibbles, and a second slot connected to the processor socket via a second subset of the first set of nibbles and connected to the first slot via the second set of nibbles.

Abstract translation: 这里描述的实施例描述了用于存储器系统的技术。 主板基板的一个实现包括第一和第二组数据线，布置成第一组半字节的第一组数据线和第二组数据线被布置成第二组半字节，其中第一和第 第二组半字节包括用于相应定时信号的相应定时线。 主板基板还包括连接到第一组数据线的处理器插座，经由第一组半字节的第一子集连接到处理器插座的第一插槽，以及经由第二组子集 第一组半字节，并通过第二组半字节连接到第一个插槽。