公开(公告)号：US07502917B2

公开(公告)日：2009-03-10

申请号：US10313277

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

IPC: G06F9/315

CPC classification number: G06F9/4812

Abstract: A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.

Abstract translation: 提供动态可选择的操作模式的处理器芯片，其中在没有外部中断的情况下执行特定的指令序列。 处理器芯片包括可以由软件设置并且使处理系统的外部中断能够被动态地启用/禁用的架构位。 当正在发出构成数据移动操作的指令序列时，构造的位被切换到中断禁止状态，使得指令序列的执行在没有外部中断的情况下发生。 在执行指令序列之后，构造的位被切换到中断使能状态，这导致指令执行受到外部中断。

公开(公告)号：US07493417B2

公开(公告)日：2009-02-17

申请号：US10318515

申请日：2002-12-12

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

IPC: G06F15/16

CPC classification number: G06F15/167

Abstract: Processor communication registers (PCRs) contained in each processor within a multiprocessor system and interconnected by a specialized bus provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs utilizing communication over the specialized bus, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract translation: 处理器通信寄存器（PCR）包含在多处理器系统中的每个处理器中并由专用总线互连提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器利用专用总线上的通信在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据内的变化，并绕过高速缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。

公开(公告)号：US20080209163A1

公开(公告)日：2008-08-28

申请号：US12118199

申请日：2008-05-09

Applicant: Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  Vicente Enrique Chung ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC: G06F15/76

CPC classification number: G06F15/8007

Abstract: A processor book designed to support both commercial workloads and technical workloads based on a dynamic or static mechanism of reconfiguring the external wiring interconnect. The processor book is configured as a building block for commercial workload processing systems with external connector buses (ECBs). The processor book is also provided with routing logic to enable to ECBs to be utilized for either book-to-book routing or routing within the same processor book. A table specific wiring scheme is provided for coupling the ECBs running off the chips of one MCM to the chips of the second MCM on the processor book so that the chips of the first MCM are connected directly to the chips of a second MCM that is logically furthest away and vice versa. Once the wiring of the ECBs are completed according to the wiring scheme, the operational and functional characteristics reflect those of a processor book configured for technical workloads.

Abstract translation: 基于重新配置外部接线互连的动态或静态机制，处理器书旨在支持商业工作负载和技术工作负载。 处理器书被配置为具有外部连接器总线（ECB）的商业工作负载处理系统的构建块。 处理器手册还提供了路由逻辑，以使ECB能够用于同一处理器书中的书本到书籍路由或路由。 提供了一种表格特定的布线方案，用于将一个MCM的芯片上运行的ECB与处理器簿上的第二个MCM的芯片耦合，使得第一个MCM的芯片直接连接到逻辑上的第二个MCM的芯片 最远的地方，反之亦然。 一旦根据布线方案完成了ECB的接线，则其操作和功能特征反映了为技术工作负载配置的处理器书。

公开(公告)号：US20080140943A1

公开(公告)日：2008-06-12

申请号：US12034769

申请日：2008-02-21

Applicant: Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

IPC: G06F12/00

CPC classification number: G06F12/0897 ,  G06F12/0804

Abstract: A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.

Abstract translation: 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失或数据在RC写入权限获得之前状态时，不会检索高速缓存行的数据。

公开(公告)号：US07089364B2

公开(公告)日：2006-08-08

申请号：US10825188

申请日：2004-04-15

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Hugh Shen ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Hugh Shen ,  Derek Edward Williams

IPC: G06F12/12

CPC classification number: G06F12/0897 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3834 ,  G06F12/0804

Abstract: A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.

Abstract translation: 一种方法和处理器系统，其基本上增强了存储队列条目的存储收集能力，以便能够在该条目被选择用于发送之前收集最大数量的接近时间存储操作。 为每个条目提供一个计数器，以跟踪从上次收集到条目的时间。 当计数器达到阈值饱和点之前没有发生新的聚合时，该信号将被发出准备就绪。 通过在计数器到期之前定义最佳阈值饱和点，为入口提供足够的时间来收集即时存储操作。 当某些条件发生时，该条目可能被视为有资格进行选择，包括条目变满，发出屏障操作和计数器饱和。 计数器的使用增加了存储队列条目完成收集足够的存储操作以在将该条目分派到RC机器之前更新整个高速缓存行的能力。

公开(公告)号：US07047320B2

公开(公告)日：2006-05-16

申请号：US10339724

申请日：2003-01-09

Applicant: Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

IPC: G06F3/00

CPC classification number: G06F13/124 ,  G06F12/0835

Abstract: An integrated circuit, such as a processing unit, includes a substrate and integrated circuitry formed in the substrate. The integrated circuitry includes a processor core that executes instructions, an interconnect interface, coupled to the processor core, that supports communication between the processor core and a system interconnect external to the integrated circuit, and at least a portion of an external communication adapter, coupled to the processor core, that supports input/output communication via an input/output communication link.

Abstract translation: 诸如处理单元的集成电路包括衬底和形成在衬底中的集成电路。 集成电路包括执行指令的处理器核心，耦合到处理器核心的互连接口，其支持处理器核心与集成电路外部的系统互连之间的通信，以及外部通信适配器的至少一部分，耦合 通过输入/输出通信链路支持输入/输出通信的处理器核心。

公开(公告)号：US07039760B2

公开(公告)日：2006-05-02

申请号：US10425443

申请日：2003-04-28

Applicant: Ravi Kumar Arimilli ,  John David McCalpin ,  Francis Patrick O'Connell ,  William John Starke

Inventor： Ravi Kumar Arimilli ,  John David McCalpin ,  Francis Patrick O'Connell ,  William John Starke

IPC: G06F12/00

CPC classification number: G06F12/123 ,  G06F12/127

Abstract: A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

Abstract translation: 一种用于在数据处理系统中管理高速缓存行的方法和装置。 使用专用寄存器，其中该寄存器可以由用户代码和操作系统代码来操作以设置优先级，诸如针对应用程序线程的2级缓存管理策略偏好。 这些偏好可以被动态设置，并且使用仲裁机制来最好地满足具有单个聚合偏好的多个线程的偏好。 会员使用最近最少使用的树来表示。 最近使用的树具有一组以层次结构形成到成员高速缓存行的路径的节点。 所选节点的状态在最近最少使用的树中的节点集合内被有选择地偏置。 在选择的节点以下的级别上的至少一个节点在管理高速缓存行时被排除。 以这种方式，当替换高速缓冲存储器中的高速缓存行时，成员可以偏向于或被选择为受害者。

公开(公告)号：US07007128B2

公开(公告)日：2006-02-28

申请号：US10752835

申请日：2004-01-07

Applicant: Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Jerry Don Lewis ,  Vicente Enrique Chung ,  Jody Bern Joyner

IPC: G06F13/00

CPC classification number: G06F13/4027

Abstract: A data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one implementation, a data processing system includes at least first through third processing units, data storage coupled to the plurality of processing units, and an interconnect fabric. The interconnect fabric includes at least a first data bus coupling the first processing unit to the second processing unit and a second data bus coupling the third processing unit to the second processing unit so that the first and third processing units can transmit data traffic to the second processing unit. The data processing system further includes a control channel coupling the first and third processing units. The first processing unit requests approval from the third processing unit via the control channel to transmit a data communication to the second processing unit, and the third processing unit approves or delays transmission of the data communication in a response transmitted via the control channel.

Abstract translation: 数据互连和路由机制减少数据通信延迟，支持基于处理器活动级别/流量的动态路由确定，并实现支持通信频率可扩展改进的架构。 在一个实现中，数据处理系统至少包括第一到第三处理单元，耦合到多个处理单元的数据存储器和互连结构。 所述互连结构至少包括将所述第一处理单元耦合到所述第二处理单元的第一数据总线和将所述第三处理单元耦合到所述第二处理单元的第二数据总线，使得所述第一处理单元和所述第三处理单元可以向第二处理单元 处理单元。 数据处理系统还包括耦合第一和第三处理单元的控制通道。 第一处理单元经由控制信道从第三处理单元请求批准，以将数据通信发送到第二处理单元，并且第三处理单元在经由控制信道发送的响应中批准或延迟数据通信的传输。

公开(公告)号：US06920514B2

公开(公告)日：2005-07-19

申请号：US10268739

申请日：2002-10-10

Applicant: Ravi Kumar Arimilli ,  Derek Edward Williams

Inventor： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC: G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F9/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/0815

Abstract: A data processing system includes a global promotion facility and a plurality of processing units coupled by an interconnect. At least one processing unit among the plurality of processing units includes one or more second caches having cache arrays in which instructions and operand data are cached, an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a promotion bit field within the global promotion facility exclusive of at least one other processing unit, and a promotion cache separate from the one or more second caches. In response to acquisition of the promotion bit field by the first processor, the promotion cache of the first processor stores the promotion bit field separately from instructions and operand data.

Abstract translation: 数据处理系统包括全球推广设施和通过互连耦合的多个处理单元。 多个处理单元中的至少一个处理单元包括具有高速缓存阵列的一个或多个第二高速缓冲存储器，其中指令和操作数据被缓存，指令排序单元，执行单元，执行获取指令以获取内部的提升位字段 全球推广设施，不包括至少一个其他处理单元，以及与所述一个或多个第二高速缓存分开的升级缓存。 响应于由第一处理器获取促销位字段，第一处理器的升级缓存存储与指令和操作数数据分开的促销位字段。

公开(公告)号：US06915390B2

公开(公告)日：2005-07-05

申请号：US10313281

申请日：2002-12-05

Applicant: Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

Inventor： Ravi Kumar Arimilli ,  Benjiman Lee Goodman ,  Jody Bern Joyner

IPC: G06F9/312 ,  G06F9/315 ,  G06F9/38 ,  G06F12/00

CPC classification number: G06F9/30087 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3877

Abstract: A processing state that enables a processor to resume processing operations before completion of a processor-issued data move operation. The processor executes instructions specifying a data clone operation and delays subsequent instruction execution while waiting for a receipt of an indication that the data clone operation has completed. In response to the instructions, a memory cloner issues a series of naked write operations targeting the destination memory location and tracks receipt of Null responses for each of the naked write operations. When a Null response has been received for each of the naked write operations, the memory cloner transmits an acknowledgment to the processor indicating that the write operation is architecturally complete before the actual data move has completed. In response to receiving the acknowledgment, the processor resumes execution of subsequent instructions in the instruction stream.

Abstract translation: 处理状态，使得处理器能够在完成处理器发出的数据移动操作之前恢复处理操作。 处理器执行指示数据克隆操作的指令，并且在等待接收到数据克隆操作已经完成的指示的同时延迟后续指令执行。 响应于指令，存储器克隆器发出针对目的地存储器位置的一系列裸写操作，并跟踪每个裸写操作的Null响应的接收。 当对于每个裸写操作已经接收到空响应时，存储器克隆器在实际数据移动完成之前向处理器发送确认，指示写操作在架构上是完整的。 响应于接收到确认，处理器恢复执行指令流中的后续指令。