公开(公告)号：US5828230A

公开(公告)日：1998-10-27

申请号：US775425

申请日：1997-01-09

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  H03K19/17792

摘要： A two-turn programmable routing structure is provided for a programmable logic device that provides a high degree of routing flexibility, with lane-changing capability, while requiring a relatively small diffusion surface area. One routing structure according to the invention provides lane-changing capability for every interconnect line in the structure and a fast path for each interconnect line running straight through the structure. The routing structure preferably comprises a unitary elongated diffusion area separated by voltage-controlled transistor gates into serially arrayed adjacent diffusion regions. The sequential diffusion regions are connected to interconnect lines having assigned directions, and can be grouped into sets of N directions, where N is a multiple of eight. The directions associated with the set of diffusion regions follow specified rules that impart the diffusion-sharing, lane-changing, and fast-path capabilities of the routing structure of the invention.

摘要翻译： 为可编程逻辑器件提供双转可编程布线结构，其提供具有通道改变能力的高度的布线灵活性，同时需要相对小的扩散表面积。 根据本发明的一个路由结构为结构中的每个互连线提供通道改变能力，并且为贯穿该结构的每个互连线提供快速路径。 路由结构优选地包括由电压控制的晶体管栅极分离为串联排列的相邻扩散区域的整体细长扩散区域。 连续扩散区域连接到具有分配方向的互连线，并且可以被分组为N个方向的集合，其中N是8的倍数。 与扩散区组相关联的方向遵循赋予本发明的路由结构的扩散共享，通道改变和快速路径能力的特定规则。

公开(公告)号：US5818730A

公开(公告)日：1998-10-06

申请号：US761113

申请日：1996-12-05

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/177 ,  G06F17/50

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： A structure and method are provided for designing the architecture of a routing structure in a programmable logic device that maximizes the number of possible paths for an available diffusion area. The method comprises steps for selecting wire directions for a plurality of wires interconnectible at a unitary diffusion area of an integrated circuit device or portion thereof. The steps of the inventive method result in a highly alternated array of wire directions, including serial sets of four wires composed of four wires extending in four compass directions. In one embodiment of the inventive method, the first two wire directions are repeated from set to set, while the second two wire directions are alternated. A second embodiment with a repeating pattern of 24 wire directions is also disclosed.

摘要翻译： 提供了一种结构和方法，用于设计可编程逻辑器件中的路由结构的架构，其使可用扩散区域的可能路径的数量最大化。 该方法包括用于选择在集成电路器件或其一部分的单一扩散区域可互连的多条导线的线方向的步骤。 本发明方法的步骤导致线交替方向的高度交替排列，包括由在四个罗盘方向上延伸的四根线组成的四根线的串联组。 在本发明方法的一个实施例中，从设定到第二两个方向重复第一个两个方向，而第二个两个方向是交替的。 还公开了具有24线方向的重复图案的第二实施例。

公开(公告)号：US5517135A

公开(公告)日：1996-05-14

申请号：US507626

申请日：1995-07-26

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： H03K19/0185 ,  H03K19/0175

CPC分类号： H03K19/018592

摘要： A bidirectional tristate buffer includes a default input such that the signal applied to one of the lines connected to the bidirectional buffer is always applied to the input terminal of a buffer element in the bidirectional buffer and applied by the output terminal of the buffer element to any load which may be driven by the buffer output terminal. In a preferred embodiment, the tristate bidirectional buffer with default input requires only four transistors plus the transistors which comprise the buffer element and memory cells for controlling the direction.

摘要翻译： 双向三态缓冲器包括默认输入，使得施加到连接到双向缓冲器的一条线路的信号总是被施加到双向缓冲器中的缓冲器元件的输入端子，并由缓冲器元件的输出端子施加到任何 可由缓冲器输出端驱动的负载。 在优选实施例中，具有默认输入的三态双向缓冲器仅需要四个晶体管加上包括用于控制方向的缓冲元件和存储单元的晶体管。

公开(公告)号：US5163712A

公开(公告)日：1992-11-17

申请号：US783309

申请日：1991-10-28

申请人： David R. Sabo ,  Steven P. Young

发明人： David R. Sabo ,  Steven P. Young

IPC分类号： F16L23/00 ,  F16L23/02 ,  F16L23/028 ,  F16L27/08

CPC分类号： F16L23/0286

摘要： A rotatable vacuum flange includes a flange ring having a recess, an insert mounted in the recess in the flange ring, the insert including a seal portion and being adapted for vacuum-tight attachment to a vacuum conduit, and a wire spring positioned between the flange ring and the insert. The wire spring retains the insert in the recess in the flange ring and permits rotation of the insert relative to the flange ring. The flange ring and the insert include grooves located in opposing alignment to receive the wire spring.

摘要翻译： 可旋转的真空凸缘包括具有凹部的凸缘环，安装在凸缘环中的凹部中的插入件，插入件包括密封部分并且适于真空密封地附接到真空导管，以及定位在凸缘之间的线弹簧 环和插入。 线弹簧将插入件保持在凸缘环中的凹槽中，并允许插入件相对于凸缘环的旋转。 凸缘环和插入件包括位于相对对准以容纳线弹簧的槽。

公开(公告)号：US09411554B1

公开(公告)日：2016-08-09

申请号：US12417046

申请日：2009-04-02

申请人： Steven P. Young ,  Brian C. Gaide

发明人： Steven P. Young ,  Brian C. Gaide

IPC分类号： G06F7/52 ,  G06F7/53

CPC分类号： G06F7/5324 ,  G06F7/53

摘要： A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.

摘要翻译： 符号乘法器电路包括基本相似的逻辑块的二维阵列。 每个逻辑块可编程以实现第一和第二输入的四个乘法函数中的任何一个，其中：第一和第二输入都被签名; 第一和第二输入都是无符号的; 第一个输入被签名，第二个输入是无符号的; 第一个输入是无符号的，第二个输入被签名。 每个逻辑块包括子行的行和列，例如逻辑与门和全加法器。 每个逻辑块的一行和一列包括可编程的可逆AND门，其中行和列被独立地控制。 对逻辑块进行编程以执行所有这四个功能的能力使逻辑块的行和列的组合能够构建几乎任何大小的大型有符号乘法器。

公开(公告)号：US09058454B1

公开(公告)日：2015-06-16

申请号：US12570637

申请日：2009-09-30

申请人： Steven P. Young ,  James Karp ,  Michael J. Hart

发明人： Steven P. Young ,  James Karp ,  Michael J. Hart

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5068 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/78

摘要： A method and apparatus to provide a power segmentation architecture that substantially eliminates the routing and area penalties associated with conventional power segmentation architectures. Power switching components are configured within the external interconnect portion of the integrated circuit (IC) to reduce the number of inter-layer interconnects that must be traversed in order to programmably supply operational power to the various device segments of the IC. A system-in-package (SIP) integration approach is alternately taken, whereby the power switching components utilized within the power segmentation architecture are conveniently allocated among the base or stacked die to reduce the number of inter-layer interconnects. The power switching components may also be implemented off-chip as discrete switching components such as a transistor or a micro-miniature switch/relay.

摘要翻译： 一种提供功率分配架构的方法和装置，其基本上消除了与常规功率分配架构相关联的路由和区域损失。 功率开关部件配置在集成电路（IC）的外部互连部分内，以减少必须穿过的层间互连的数量，以便可编程地向IC的各种器件段提供工作功率。 交替采用系统级封装（SIP）集成方法，由此在功率分配架构内使用的功率开关组件方便地分配在基极或堆叠管芯中，以减少层间互连的数量。 功率开关组件也可以作为诸如晶体管或微型微型开关/继电器之类的离散开关组件而非芯片地实现。

公开(公告)号：US20130320714A1

公开(公告)日：2013-12-05

申请号：US13960844

申请日：2013-08-07

申请人： Steven P. Young

发明人： Steven P. Young

IPC分类号： B62J17/00

CPC分类号： B62K5/027 ,  B60G13/08 ,  B60G17/0162 ,  B60G21/073 ,  B60G2300/122 ,  B60G2300/45 ,  B60K17/356 ,  B60W2300/156 ,  B60W2510/20 ,  B60Y2200/223 ,  B62J15/02 ,  B62J17/00 ,  B62K5/10

摘要： A wheel suspension system for a three-wheeled motorcycle or “trike” includes parallel wheels mounted on vertically pivoting suspension arms governed by hydraulic pistons. The pistons have upper liquid reservoirs that are interconnected through a valve system, which interconnects the upper reservoirs when the trike is in motion, allowing opposing vertical wheel movements when banking through turns, and prevents liquid exchange when the trike is stopped, thereby holding the motorcycle upright, Embodiments include a manual and/or automatic valve control. A threshold switching speed for an automatic controller can be factory set and/or user adjustable. The pistons can include directly interconnected lower fluid reservoirs. A shock-absorbing reservoir can allow transient vertical movement of both wheels to absorb shocks. A cover system can emulate the appearance of saddle bags and can appear to be covering only a single wheel.

摘要翻译： 用于三轮摩托车或“三轮车”的车轮悬挂系统包括安装在由液压活塞控制的垂直枢转悬挂臂上的平行轮。 活塞具有通过阀系统相互连接的上部液体储存器，当三通阀运动时，将上部储存器互连，允许相反的垂直车轮运动，当车辆转弯时，可防止三轮车停止时进行液体交换，从而保持摩托车 实施例包括手动和/或自动阀控制。 自动控制器的阈值切换速度可以在出厂设置和/或用户可调。 活塞可以包括直接互连的下部流体储存器。 减震水箱可以允许两个轮子的瞬时垂直运动以吸收冲击。 盖系统可以模拟鞍形袋的外观，并且似乎只能覆盖一个车轮。

公开(公告)号：US08301988B1

公开(公告)日：2012-10-30

申请号：US13005475

申请日：2011-01-12

申请人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

发明人： Warren E. Cory ,  David P. Schultz ,  Steven P. Young

IPC分类号： H03M13/00

CPC分类号： H03M13/27 ,  H03M13/19 ,  H03M13/45

摘要： An apparatus for error checking is described. The apparatus includes a matrix having a plurality of bit position columns and rows, where the bit position columns are equal in number to data bits of a word length, the word length for a word serial transmission of a data vector, where the bit position columns are one each for each data bit. The bit position rows are equal in number to syndrome bits, and the bit position rows are one each for each syndrome bit. A portion of the bit position columns are allocated to parity bits for a selected word of the data vector, where the portion of the bit position columns for the selected word are one each for each parity bit allocated to the selected word.

摘要翻译： 描述用于错误检查的装置。 该装置包括具有多个位位列和行的矩阵，其中位位列的数量与字长度的数据位相等，数据向量的字串行传输的字长，其中位位置列 每个数据位都是一个。 位位置行的数量与校正子位数相等，并且位位置行对于每个校正子位都是一个。 比特位列的一部分被分配给数据向量的所选字的奇偶校验位，其中所选字的位位列的部分对于分配给所选字的每个奇偶校验位都是一个。

公开(公告)号：US08120382B2

公开(公告)日：2012-02-21

申请号：US12718848

申请日：2010-03-05

申请人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

发明人： Trevor J. Bauer ,  Ramakrishna K. Tanikella ,  Steven P. Young

IPC分类号： H03K19/177

CPC分类号： H03K19/17796

摘要： A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks (148), and each of the first and second logic columns includes programmable logic blocks. Each programmable interconnect block provides a plurality of first input and output ports on a first side and a plurality of second input and output ports on a second side. The first ports and the first side of each of the programmable interconnect blocks physically mirror the second ports and the second side of the programmable interconnect block. The ports of the programmable interconnect blocks are coupled to the ports of the programmable logic blocks in the first and second logic columns.

摘要翻译： 具有镜像互连结构的可编程集成电路（IC）。 IC包括水平布置的多个布置。 每个布置包括第一逻辑列，互连列和第二逻辑列。 每个互连列包括可编程互连块（148），并且第一和第二逻辑列中的每一个包括可编程逻辑块。 每个可编程互连块在第一侧上提供多个第一输入和输出端口以及在第二侧上提供多个第二输入和输出端口。 每个可编程互连块的第一端口和第一侧物理地镜像可编程互连块的第二端口和第二侧。 可编程互连块的端口耦合到第一和第二逻辑列中的可编程逻辑块的端口。

公开(公告)号：US08058897B1

公开(公告)日：2011-11-15

申请号：US12825286

申请日：2010-06-28

申请人： Weiguang Lu ,  Eric E. Edwards ,  Paul-Hugo Lamarche ,  Steven P. Young ,  Brian C. Gaide ,  Joe Eddie Leyba, II

发明人： Weiguang Lu ,  Eric E. Edwards ,  Paul-Hugo Lamarche ,  Steven P. Young ,  Brian C. Gaide ,  Joe Eddie Leyba, II

IPC分类号： H03K19/173 ,  H01L25/00

CPC分类号： H03K19/177 ,  G06F17/5054 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

摘要翻译： 配置集成电路（IC）的方法可以包括在IC的主管芯内接收配置数据。 IC可以包括主模和从模。 可以确定配置数据的主段和从段。 配置数据的从属段可以分配给IC的从属模块。