公开(公告)号：US20230082313A1

公开(公告)日：2023-03-16

申请号：US17799977

申请日：2021-02-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takuro KANEMURA

IPC: G06F7/544 ,  G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G06N3/04

Abstract: A semiconductor device with reduced power consumption that can perform a product-sum operation is provided. The semiconductor device includes first and second circuits, and the second circuit includes first and second switches, a current/voltage converter circuit, and a first transistor. The first circuit is electrically connected to a first terminal of the second circuit; a first terminal of the first switch is electrically connected to the first terminal of the second circuit; a second terminal of the first switch is electrically connected to an input terminal of the current/voltage converter circuit; an output terminal of the current/voltage converter circuit is electrically connected to a first terminal of the first transistor; a second terminal of the first transistor is electrically connected to a first terminal of the second switch; and a second terminal of the second switch is electrically connected to a second terminal of the second circuit. The first circuit has a function of retaining a plurality of pieces of first data and a function of making a current in an amount responsive to the sum of products of the plurality of pieces of first data and a plurality of pieces of second data flow to the first terminal of the second circuit when the plurality of pieces of second data are input to the first circuit.

公开(公告)号：US20230043910A1

公开(公告)日：2023-02-09

申请号：US17793104

申请日：2021-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Takuro KANEMURA

IPC: H04N5/376 ,  H01L27/30

Abstract: A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1-I2-I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

公开(公告)号：US20220294402A1

公开(公告)日：2022-09-15

申请号：US17635268

申请日：2020-08-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei TAKAHASHI ,  Takeshi AOKI ,  Munehiro KOZUMA ,  Takayuki IKEDA

IPC: H03F3/45 ,  H01L27/12 ,  H03K5/24

Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal. The semiconductor device has a function of outputting a comparison result of a signal supplied to a gate of the second transistor and a signal supplied to a gate of the third transistor, from the first output terminal and the second output terminal; and a function of changing the potential output from the first output terminal in accordance with the potential applied to a back gate of the first transistor.

公开(公告)号：US20220237440A1

公开(公告)日：2022-07-28

申请号：US17611207

申请日：2020-05-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime KIMURA ,  Munehiro KOZUMA

IPC: G06N3/063 ,  H01L27/108 ,  G06F7/492 ,  G06F7/496 ,  H01L29/786

Abstract: A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, the first circuit is electrically connected to a first wiring, and the second circuit is electrically connected to a second wiring. The first wiring is electrically connected to a first terminal of the capacitor through the first switch, and the second wiring is electrically connected to the first terminal of the capacitor through the third switch. The first terminal of the capacitor is electrically connected to a first terminal of the second switch, and a second terminal of the capacitor is electrically connected to the first amplifier circuit through the fourth switch. Current corresponding to the result of product-sum operation flows through each of the first and second wirings, and the current is converted into potentials by the first and second circuits. A difference between the converted potentials is held in the capacitor, and the difference is input to the first amplifier circuit and is output as a potential corresponding to the arithmetic operation result.

公开(公告)号：US20220173737A1

公开(公告)日：2022-06-02

申请号：US17441804

申请日：2020-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Sho NAGAO

IPC: H03K19/08 ,  H03K17/56

Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.

公开(公告)号：US20220085427A1

公开(公告)日：2022-03-17

申请号：US17420536

申请日：2020-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryota TAJIMA ,  Kei TAKAHASHI ,  Hiroki INOUE ,  Munehiro KOZUMA ,  Takahiro FUKUTOME

IPC: H01M10/44 ,  G01R31/367 ,  H02J7/00 ,  H01M10/48

Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.

公开(公告)号：US20210384751A1

公开(公告)日：2021-12-09

申请号：US17286088

申请日：2019-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kei TAKAHASHI ,  Takayuki IKEDA ,  Takanori MATSUZAKI ,  Munehiro KOZUMA ,  Hiroki INOUE ,  Ryota TAJIMA ,  Yohei MOMMA ,  Mayumi MIKAMI ,  Kazutaka KURIKI ,  Shunpei YAMAZAKI

IPC: H02J7/00

Abstract: A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.

公开(公告)号：US20210126473A1

公开(公告)日：2021-04-29

申请号：US17258957

申请日：2019-06-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Ryota TAJIMA ,  Shunpei YAMAZAKI ,  Yuki OKAMOTO

IPC: H02J7/00 ,  H01M10/42

Abstract: Safety is secured in such a manner that an anomaly of a secondary battery is detected with a protection circuit, for example, a phenomenon that lowers the safety of a secondary battery, particularly a micro short circuit, is detected early, and users are warned or the use of the secondary battery is stopped. A secondary battery protection circuit includes a first memory circuit electrically connected to a secondary battery, a comparison circuit electrically connected to the first memory circuit, a second memory circuit electrically connected to the comparison circuit, and a power-off switch electrically connected to the second memory circuit. The power-off switch is electrically connected to the secondary battery, and the first memory circuit includes a first transistor including an oxide semiconductor and retains a voltage value of the secondary battery in an analog manner.

公开(公告)号：US20170288670A1

公开(公告)日：2017-10-05

申请号：US15471516

申请日：2017-03-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA ,  Yoshiyuki KUROKAWA

IPC: H03K19/00 ,  H03K21/02 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K21/026

Abstract: Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured.

公开(公告)号：US20170141776A1

公开(公告)日：2017-05-18

申请号：US15345761

申请日：2016-11-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Munehiro KOZUMA

IPC: H03K19/177

CPC classification number: H03K19/17764 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/17792

Abstract: A semiconductor device includes a configuration memory that has functions of holding configuration data and generating a signal based on the configuration data, a context generator that has a function of generating a signal for controlling context switch, a clock generator that has a function of operating in a first mode or a second mode in accordance with the signal generated in the configuration memory, and a PLD. A clock signal is input to the context generator and the clock generator. The clock generator outputs the clock signal to the PLD in the first mode and stops outputting the clock signal to the PLD in the second mode.