公开(公告)号：US09953717B2

公开(公告)日：2018-04-24

申请号：US15292548

申请日：2016-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jagdish Sabde ,  Jayavel Pachamuthu ,  Peter Rabkin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C11/56 ,  G11C16/16

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

公开(公告)号：US09881929B1

公开(公告)日：2018-01-30

申请号：US15335850

申请日：2016-10-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Pradhyumna Ravikirthi ,  Jayavel Pachamuthu ,  Jagdish Sabde ,  Peter Rabkin

IPC: H01L27/11 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A first tier structure including a first alternating stack of first insulating layers and first sacrificial material layers is formed over a substrate. First support openings and first memory openings, filled with first support pillar structures and sacrificial pillar structures, respectively, are formed through the first tier structure. A second tier structure including a second alternating stack of second insulating layers and second sacrificial material layers is formed thereabove. Second support openings and second memory openings are formed through the second tier structure such that the second support openings do not overlap with the first support pillar structures and the second memory openings overlie the sacrificial pillar structures. Inter-tier memory openings are formed by removal of the sacrificial pillar structures. Memory stack structures and second support pillar structures are formed in the inter-tier memory openings and the second support openings, respectively.

公开(公告)号：US20170287566A1

公开(公告)日：2017-10-05

申请号：US15292548

申请日：2016-10-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jagdish Sabde ,  Jayavel Pachamuthu ,  Peter Rabkin

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.

公开(公告)号：US09711229B1

公开(公告)日：2017-07-18

申请号：US15246510

申请日：2016-08-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  H01L27/115 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/10 ,  H01L45/145 ,  H01L45/146

Abstract: Systems and methods for performing a partial block erase operation on a portion of a memory array are described. The memory array may include a plurality of vertical NAND strings in which a first set of the plurality of vertical NAND strings are connected to a first drain-side select line, a second set of the plurality of vertical NAND strings are connected to a second drain-side select line, and both the first set and the second set of vertical NAND strings are connected to one or more shared word lines. In cases where a first vertical NAND string of the first set and a second vertical NAND string of the second set are both connected to selected bit lines and the same shared word line, selectivity of memory cells may be provided by applying different voltages to the first drain-side select line and the second drain-side select line.

公开(公告)号：US20170062068A1

公开(公告)日：2017-03-02

申请号：US15352390

申请日：2016-11-15

Applicant: SanDisk Technologies LLC

Inventor： Peter Rabkin ,  Yingda Dong ,  Masaaki Higashitani

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Methods for improving channel boosting and reducing program disturb during programming of memory cells within a memory array are described. The memory array may comprise a NAND flash memory structure, such as a vertical NAND structure or a bit cost scalable (BiCS) NAND structure. In some cases, by applying continuous voltage ramping to unselected word lines during or throughout a programming operation, the boosting of channels associated with program inhibited memory cells may be improved. In one example, the slope and timing of a Vpass waveform applied to a group of unselected word lines (e.g., the neighboring word lines of the selected word line) during the programming operation may be set based on the location of the selected word line within the memory array and the locations of the group of unselected word lines within the

Abstract translation: 描述了用于在存储器阵列内的存储器单元的编程期间改进信道增强和减少编程干扰的方法。 存储器阵列可以包括NAND快闪存储器结构，诸如垂直NAND结构或位成本可缩放（BiCS）NAND结构。 在一些情况下，通过在编程操作期间或整个编程操作期间对未选择的字线施加连续电压斜坡，可以提高与编程禁止的存储器单元相关联的通道的升压。 在一个示例中，可以基于所选择的字线的位置来设置在编程操作期间施加到一组未选择字线（例如，所选字线的相邻字线）的Vpass波形的斜率和定时 存储器阵列和组内的未选择字线的位置