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公开(公告)号：US08802535B2
公开(公告)日：2014-08-12
申请号：US13461935
申请日：2012-05-02
IPC分类号： H01L21/331
CPC分类号： H01L29/772 , H01L29/66795 , H01L29/7854
摘要： Techniques for fabricating a field effect transistor (FET) device having a doped core and an undoped or counter-doped epitaxial shell are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A wafer is provided having a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon. At least one fin core is formed in the wafer. Ion implantation is used to dope the fin core. Corners of the fin core are reshaped to make the corners rounded or faceted. An epitaxial shell is grown surrounding the fin core, wherein the epitaxial shell includes a semiconductor material selected from the group consisting of silicon, silicon germanium and silicon carbon.
摘要翻译： 提供了用于制造具有掺杂芯和未掺杂或反掺杂外延壳的场效应晶体管（FET）器件的技术。 一方面，提供一种制造FET器件的方法。 该方法包括以下步骤。 提供具有选自硅，硅锗和硅碳的半导体材料的晶片。 在晶片中形成至少一个鳍芯。 离子注入用于掺杂鳍芯。 鳍芯的角部重新成形，使角落圆角或圆形。 围绕鳍芯生长外延壳，其中外延壳包括选自硅，硅锗和硅碳的半导体材料。
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公开(公告)号：US08680589B2
公开(公告)日：2014-03-25
申请号：US13372719
申请日：2012-02-14
IPC分类号： H01L21/02
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/845 , H01L27/1211 , H01L29/0665 , H01L29/42392 , H01L29/66439 , H01L29/66628 , H01L29/66772 , H01L29/78645 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire on a semiconductor substrate, forming a first gate structure on a first portion of the nanowire, forming a first protective spacer adjacent to sidewalls of the first gate structure and over portions of the nanowire extending from the first gate structure, removing exposed portions of the nanowire left unprotected by the first spacer, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a first source region and a first drain region.
摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的第一部分上形成第一栅极结构，形成与第一栅极结构的侧壁相邻的第一保护隔离层， 纳米线的部分从第一栅极结构延伸，去除未被第一间隔物保护的纳米线的暴露部分，并且在纳米线的暴露的横截面上外延生长掺杂的半导体材料，以形成第一源极区域和第一漏极区域。
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公开(公告)号：US20140021538A1
公开(公告)日：2014-01-23
申请号：US13550861
申请日：2012-07-17
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66545 , H01L29/165 , H01L29/42392 , H01L29/66795 , H01L29/785
摘要： In one aspect, a method of fabricating a nanowire FET device includes the following steps. A wafer is provided. At least one sacrificial layer and silicon layer are formed on the wafer in a stack. Fins are patterned in the stack. Dummy gates are formed over portions of the fins which will serve as channel regions, and wherein one or more portions of the fins which remain exposed will serve as source and drain regions. A gap filler material is deposited surrounding the dummy gates and planarized. The dummy gates are removed forming trenches in the gap filler material. Portions of the silicon layer (which will serve as nanowire channels) are released from the fins within the trenches. Replacement gates are formed within the trenches that surround the nanowire channels in a gate all around configuration. A nanowire FET device is also provided.
摘要翻译： 一方面，制造纳米线FET器件的方法包括以下步骤。 提供晶片。 在堆叠中的晶片上形成至少一个牺牲层和硅层。 翅片在堆叠中被图案化。 虚拟门形成在将用作沟道区域的鳍的部分上，并且其中保持暴露的鳍的一个或多个部分将用作源极和漏极区。 围绕虚拟栅极沉积间隙填充材料并进行平面化处理。 移除在间隙填充材料中形成凹槽的伪栅极。 硅层（其将用作纳米线通道）的部分从沟槽内的翅片释放。 替代栅极形成在围绕纳米线通道的沟槽内的沟槽中，全部配置。 还提供了纳米线FET器件。
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公开(公告)号：US08519479B2
公开(公告)日：2013-08-27
申请号：US12778526
申请日：2010-05-12
IPC分类号： H01L27/12
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01L21/302 , H01L21/3247 , H01L29/045 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.
摘要翻译： 提供了修改具有设置在绝缘体上的半导体的晶片的方法，并且包括分别在第一和第二晶片区域处形成分别连接到半导体焊盘的第一和第二纳米线通道，其中第二纳米线通道侧壁相对于晶体学不对准 半导体的平面超过第一纳米线通道侧壁并将半导体移向侧壁和结晶平面之间的对准状态，使得第一和第二纳米线通道之间的厚度差异反映了第二纳米线通道侧壁的较大的未对准。
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公开(公告)号：US08507892B2
公开(公告)日：2013-08-13
申请号：US13372714
申请日：2012-02-14
IPC分类号： H01L29/66
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/26586 , H01L21/31111 , H01L21/31155 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 一种形成纳米线隧道场效应晶体管器件的方法包括形成连接到第一焊盘区域和第二焊盘区域的纳米线，纳米线包括芯部分和电介质层，在纳米线的电介质层上形成栅极结构， 在所述纳米线的部分上形成第一保护隔离物，在所述暴露的纳米线和所述第一焊盘区域的第一部分中注入离子，将所述暴露的纳米线和所述第二焊盘区域的第二部分的电介质层注入， 从所述第二焊盘区域和所述第二部分去除所述暴露的纳米线的第二部分的芯部分以形成空腔，以及在所述空腔中外延生长掺杂半导体材料，以将所述纳米线的暴露的横截面与所述第二焊盘 地区。
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公开(公告)号：US20130112937A1
公开(公告)日：2013-05-09
申请号：US13292336
申请日：2011-11-09
IPC分类号： H01L29/772 , H01L21/336 , H01L29/775 , B82Y40/00 , B82Y99/00
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.
摘要翻译： 一种用于形成场效应晶体管器件的方法包括形成悬浮在衬底上的纳米线，在衬底的一部分和纳米线的一部分周围形成虚拟栅极堆叠，从纳米线的外延生长纳米线延伸部分的外延生长 暴露的纳米线部分，在衬底的暴露部分，伪栅极堆叠和纳米线延伸部分上沉积半导体材料层，以及去除半导体材料的部分以形成邻近虚拟栅极堆叠布置的侧壁接触区域， 纳米线延伸部分。
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公开(公告)号：US20120319084A1
公开(公告)日：2012-12-20
申请号：US13600598
申请日：2012-08-31
IPC分类号： H01L27/088
CPC分类号： H01L29/78696 , B82Y10/00 , B82Y40/00 , H01L21/84 , H01L27/1203 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66469 , H01L29/66772
摘要： An integrated circuit includes a plurality of gate-all-around (GAA) nanowire field effect transistors (FETs), a plurality of omega-gate nanowire FETs, and a plurality of planar channel FETs, wherein the plurality of GAA FETs, the plurality of omega-gate nanowire FETs, and the plurality of planar channel FETs are disposed on a single wafer.
摘要翻译： 集成电路包括多个栅极全能（GAA）纳米线场效应晶体管（FET），多个Ω-栅极纳米线FET和多个平面沟道FET，其中多个GAA FET，多个 ω-门纳米线FET，并且多个平面沟道FET设置在单个晶片上。
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公开(公告)号：US08324030B2
公开(公告)日：2012-12-04
申请号：US12778315
申请日：2010-05-12
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.
摘要翻译： 形成纳米线隧道场效应晶体管（FET）器件的方法包括形成由第一焊盘区域和第二焊盘区域悬挂的纳米线，在纳米线的一部分周围形成栅极，形成邻近栅极侧壁的保护隔离层 结构和纳米线的周围部分从栅极结构延伸，将离子注入暴露的纳米线的第一部分中，去除暴露的纳米线的第二部分以形成由栅极结构包围的纳米线的核心部分限定的空腔，以及 所述间隔物暴露所述衬底的硅部分，以及从所述纳米线，所述第二焊盘区域和暴露的硅部分的暴露截面外延生长所述腔中的掺杂半导体材料，以将所述纳米线的暴露的横截面与 第二垫区域。
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公开(公告)号：US20120273761A1
公开(公告)日：2012-11-01
申请号：US13541022
申请日：2012-07-03
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/78696
摘要： A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.
摘要翻译： 纳米线隧道场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有第一远端和第二远端的硅部分，硅部分被围绕硅部分周向设置的栅极结构围绕，漏极区域包括 从第一远端延伸的掺杂硅部分，布置在沟道区域中的掺杂硅部分的一部分，由硅部分的第二远端限定的空腔和栅极结构的内径，以及源区域， 从空腔中的硅部分的第二远端外延延伸的掺杂外延硅部分，第一焊盘区域和硅衬底的一部分。
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公开(公告)号：US08263477B2
公开(公告)日：2012-09-11
申请号：US12684331
申请日：2010-01-08
IPC分类号： H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/7391 , H01L21/2007 , H01L21/76254 , H01L29/66227
摘要： A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.
摘要翻译： 制造用于制造PiN异质结隧道场效应晶体管（TFET）的结构的方法包括在硅晶片中形成取向沟槽; 在硅晶片中形成硅锗（SiGe）生长沟槽; 在SiGe生长沟槽中生长p型SiGe区域; 在对准沟槽和p型SiGe区域上形成第一氧化物层; 在所述硅晶片中形成氢注入区域，所述氢注入区域将所述硅晶片分成上硅区和下硅区; 将第一氧化物层接合到位于处理晶片上的第二氧化物层，形成包含第一氧化物层和第二氧化物层的键合氧化物层; 以及在所述氢注入区域处从所述上硅区域分离所述下硅区域。
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