公开(公告)号：US20120126367A1

公开(公告)日：2012-05-24

申请号：US13360277

申请日：2012-01-27

申请人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

发明人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L23/525

CPC分类号： H01L23/5252 ,  H01L21/76823 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

公开(公告)号：US08183145B2

公开(公告)日：2012-05-22

申请号：US11870551

申请日：2007-10-11

申请人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Ying Li ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76846 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench.

摘要翻译： 方法和结构。 形成接触结构的方法包括将硅化物层沉积到基底上; 在所述硅化物层的第一表面上沉积电绝缘层; 通过延伸到第一表面的绝缘层形成通孔; 沉积覆盖所述通孔的底部和至少一个垂直壁的导电层; 从底部去除导电层; 并且用直接与硅化物层接触的铝填充该通孔。 一种结构包括：设置在基板上的硅化物层; 设置在所述硅化物层上的电绝缘层; 延伸穿过绝缘层并直接接触硅化物层的铝塞; 以及设置在插塞和绝缘层之间的导电层。 还包括其中铝层从硅化物层和沟槽的至少一个侧壁选择性地生长的方法。

公开(公告)号：US20110079874A1

公开(公告)日：2011-04-07

申请号：US12574926

申请日：2009-10-07

申请人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

发明人： Terence L. Kane ,  Michael P. Tenney ,  Yun-Yu Wang ,  Keith Kwong Hon Wong

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L21/76823 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

摘要翻译： 反熔丝结构和在反熔丝结构内形成接触的方法。 反熔丝结构包括具有上覆金属层的基板，形成在金属层的上表面上的电介质层，以及由通过电介质层蚀刻到金属层中的接触孔内的接触材料形成的接触。 接触通孔在接触通孔的底表面处包括金属材料，并且在金属材料的顶部上包​​括未处理或部分处理的金属前体。

公开(公告)号：US20100187610A1

公开(公告)日：2010-07-29

申请号：US12359520

申请日：2009-01-26

申请人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

发明人： Unoh Kwon ,  Siddarth A. Krishnan ,  Takashi Ando ,  Michael P. Chudzik ,  Martin M. Frank ,  William K. Henson ,  Rashmi Jha ,  Yue Liang ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/4966 ,  H01L29/517

摘要： A semiconductor device includes: a semiconductor substrate; a PFET formed on the substrate, the PFET includes a SiGe layer disposed on the substrate, a high-K dielectric layer disposed on the SiGe layer, a first metallic layer disposed on the high-k dielectric layer, a first intermediate layer disposed on the first metallic layer, a second metallic layer disposed on the first intermediate layer, a second intermediate layer disposed on the second metallic layer, and a third metallic layer disposed on the second intermediate layer; an NFET formed on the substrate, the NFET includes the high-k dielectric layer, the high-k dielectric layer being disposed on the substrate, the second intermediate layer, the second intermediate layer being disposed on the high-k dielectric layer, and the third metallic layer, the third metallic layer being disposed on the second intermediate layer. Alternatively, the first metallic layer is omitted. A method to fabricate the device includes providing SiO2 and alpha-silicon layers or a dBARC layer.

摘要翻译： 半导体器件包括：半导体衬底; 形成在衬底上的PFET，PFET包括设置在衬底上的SiGe层，设置在SiGe层上的高K电介质层，设置在高k电介质层上的第一金属层，设置在第一中间层上的第一中间层 第一金属层，设置在第一中间层上的第二金属层，设置在第二金属层上的第二中间层和设置在第二中间层上的第三金属层; 形成在衬底上的NFET，NFET包括高k电介质层，高k电介质层设置在衬底上，第二中间层，第二中间层设置在高k电介质层上，并且 第三金属层，第三金属层设置在第二中间层上。 或者，省略第一金属层。 制造该器件的方法包括提供SiO 2和α-硅层或dBARC层。

公开(公告)号：US20100143649A1

公开(公告)日：2010-06-10

申请号：US12706108

申请日：2010-02-16

申请人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

发明人： Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Chih-Chao Yang ,  Haining S. Yang

IPC分类号： B32B3/10

CPC分类号： C25D5/02 ,  Y10T428/24331 ,  Y10T428/24917

摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.

摘要翻译： 公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料 没有接缝和/或空隙。 此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层 金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

公开(公告)号：US07659199B2

公开(公告)日：2010-02-09

申请号：US12062592

申请日：2008-04-04

申请人： Robert J. Purtell ,  Keith Kwong Hon Wong

发明人： Robert J. Purtell ,  Keith Kwong Hon Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L29/7833

摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.

摘要翻译： 公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。 更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。 然而，在沉积第二金属层之前，保护层暴露于空气中。 这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。 结果是对于n-FET性能最佳的更强的硅化物。 此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在 栅极导体和侧壁间隔件，以避免硅桥接。

公开(公告)号：US20090294920A1

公开(公告)日：2009-12-03

申请号：US12132146

申请日：2008-06-03

申请人： Michael P. Chudzik ,  Rashmi Jha ,  Naim Moumen ,  Keith Kwong Hon Wong ,  Ying H. Tsang

发明人： Michael P. Chudzik ,  Rashmi Jha ,  Naim Moumen ,  Keith Kwong Hon Wong ,  Ying H. Tsang

IPC分类号： H01L23/58 ,  H01L21/311

CPC分类号： H01L21/31133 ,  H01L21/31127 ,  H01L21/31138

摘要： Methods for forming a front-end-of-the-line (FEOL) dual high-k gate using a photoresist mask and structures thereof are disclosed. One embodiment of the disclosed method includes depositing a high-k dielectric film on a substrate of a FEOL CMOS structure followed by depositing a photoresist thereon; patterning the high-k dielectric according to the photoresist; and removing the photoresist thereafter. The removing of the photoresist includes using an organic solvent followed by removal of any residual photoresist including organic and/or carbon film. The removal of residual photoresist may include a degas process, alternatively known as a bake process. Alternatively, a nitrogen-hydrogen forming gas (i.e., a mixture of nitrogen and hydrogen) (N2/H2) or ammonia (NH3) may be used to remove the photoresist mask. With the use of the plasma nitrogen-hydrogen forming gas (N2/H2) or a plasma ammonia (NH3), no apparent organic residual is observed.

摘要翻译： 公开了使用光致抗蚀剂掩模及其结构形成前端（FEOL）双高k栅极的方法。 所公开方法的一个实施例包括在FEOL CMOS结构的衬底上沉积高k电介质膜，然后在其上沉积光致抗蚀剂; 根据光致抗蚀剂图案化高k电介质; 之后除去光致抗蚀剂。 去除光致抗蚀剂包括使用有机溶剂，然后除去包括有机和/或碳膜的残留光致抗蚀剂。 去除残留的光致抗蚀剂可以包括脱气工艺，或称为烘烤工艺。 或者，可以使用形成氮气的气体（即，氮气和氢气的混合物）（N 2 / H 2）或氨（NH 3）以除去光致抗蚀剂掩模。 通过使用等离子体形成氮气的气体（N 2 / H 2）或等离子体氨（NH 3），没有观察到明显的有机残留。

公开(公告)号：US07622386B2

公开(公告)日：2009-11-24

申请号：US11567517

申请日：2006-12-06

申请人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

发明人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.

摘要翻译： 形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室， 将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。

公开(公告)号：US07598545B2

公开(公告)日：2009-10-06

申请号：US11111592

申请日：2005-04-21

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：US20090111235A1

公开(公告)日：2009-04-30

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。