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    SEMICONDUCTOR DEVICE
    71.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210174857A1

    公开(公告)日：2021-06-10

    申请号：US17048330

    申请日：2019-04-22

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hajime KIMURA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

    IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/108 ,  H01L27/12

    Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

    SEMICONDUCTOR DEVICE
    73.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190287974A1

    公开(公告)日：2019-09-19

    申请号：US16431778

    申请日：2019-06-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/108 ,  H01L27/12 ,  H01L27/1156 ,  H01L27/11551 ,  H01L27/11521 ,  H01L27/06

    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

    SEMICONDUCTOR DISPLAY DEVICE
    74.
    发明申请
    SEMICONDUCTOR DISPLAY DEVICE 审中-公开

    公开(公告)号：US20190067336A1

    公开(公告)日：2019-02-28

    申请号：US16107536

    申请日：2018-08-21

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei YAMAZAKI ,  Satoshi MURAKAMI ,  Masahiko HAYAKAWA ,  Kiyoshi KATO ,  Mitsuaki OSAME

    IPC: H01L27/12 ,  H01L33/52 ,  H01L27/32 ,  G02F1/1362 ,  H01L51/52 ,  H01L27/13

    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is fanned so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

    SEMICONDUCTOR DEVICE
    76.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170272079A1

    公开(公告)日：2017-09-21

    申请号：US15610705

    申请日：2017-06-01

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

    IPC: H03K19/177 ,  H03K19/173

    Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
    78.
    发明申请
    SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
    半导体器件和电子器件

    公开(公告)号：US20170062482A1

    公开(公告)日：2017-03-02

    申请号：US15245310

    申请日：2016-08-24

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuto YAKUBO ,  Shuhei NAGATSUKA

    IPC: H01L27/12 ,  H01L23/544 ,  H01L29/66 ,  H01L29/786

    CPC classification number: H01L27/1225 ,  H01L23/544 ,  H01L27/1207 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2223/54453

    Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.

    Abstract translation: 提供在其制造过程中不容易被ESD损坏的半导体器件。 带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层被提供以与切割线重叠。 在诸如晶体管的半导体器件周围设置一个其带隙大于或等于2.5eV且小于或等于4.2eV，优选大于或等于2.7eV且小于或等于3.5eV的层。 该层可以处于浮置状态或者可以被提供特定的电位。

    MICROCONTROLLER AND METHOD FOR MANUFACTURING THE SAME
    79.
    发明申请
    MICROCONTROLLER AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    微控制器及其制造方法

    公开(公告)号：US20170038826A1

    公开(公告)日：2017-02-09

    申请号：US15299579

    申请日：2016-10-21

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tatsuji NISHIJIMA ,  Hidetomo KOBAYASHI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

    Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

    Abstract translation: 提供以低功耗模式工作的微控制器。 微控制器包括CPU，存储器和诸如定时器电路的外围电路。 外围电路中的寄存器设置在与总线线路的接口中。 提供用于控制电源控制的电源门。 微控制器不仅可以在所有电路都有效的正常工作模式下工作，而且还可以在一些电路处于活动状态的低功耗模式下工作。 在诸如CPU的寄存器的寄存器中提供易失性存储器和非易失性存储器。 在电源停止之前，易失性存储器中的数据被备份在非易失性存储器中。 在操作模式返回到正常模式的情况下，当再次开始供电时，非易失性存储器中的数据被写回到易失性存储器中。

    MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    80.
    发明申请
    MEMORY DEVICE AND SEMICONDUCTOR DEVICE 审中-公开
    存储器件和半导体器件

    公开(公告)号：US20170033110A1

    公开(公告)日：2017-02-02

    申请号：US15292362

    申请日：2016-10-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

    IPC: H01L27/105 ,  H01L27/12 ,  H01L29/786

    Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

    Abstract translation: 本发明的目的是提供一种能够抑制功耗的存储器件和包括存储器件的半导体器件。 作为用作保持蓄积在用作存储元件的晶体管中的电荷的开关元件，为存储器件中的每个存储单元提供包括作为有源层的氧化物半导体膜的晶体管。 用作存储元件的晶体管具有第一栅电极，第二栅电极，位于第一栅电极和第二栅电极之间的半导体膜，位于第一栅电极和半导体膜之间的第一绝缘膜， 位于第二栅电极和半导体膜之间的第二绝缘膜，以及与半导体膜接触的源电极和漏电极。

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