公开(公告)号：US07468537B2

公开(公告)日：2008-12-23

申请号：US11012469

申请日：2004-12-15

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a），以及其制造方法（202），其中p型分离区域（130）形成在n埋层（108）和 晶体管背栅极（126），以增加击穿电压性能而不增加外延厚度。

公开(公告)号：US07427795B2

公开(公告)日：2008-09-23

申请号：US10880907

申请日：2004-06-30

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L31/119

CPC分类号： H01L29/7816 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) over a substrate (104), and a drain-extended MOS transistor (T1, T2) is formed in the epitaxial silicon layer (106). The p-buried layer (130) may be formed above an n-buried layer (120) in the substrate (104) for high-side driver transistor (T2) applications, wherein the p-buried layer (130) extends between the drain-extended MOS transistor (T2) and the n-buried layer (120) to inhibit off-state breakdown between the source (154) and drain (156).

摘要翻译： 描述了漏极扩散MOS晶体管（T 1，T 2）和半导体器件（102）及其制造方法（202），其中在形成外延硅之前形成p埋层（130） 106），并且在外延硅层（106）中形成漏极扩展MOS晶体管（T 1，T 2）。 p埋层（130）可以形成在用于高侧驱动晶体管（T 2）应用的衬底（104）中的n掩埋层（120）上方，其中p埋层（130）在 漏极扩展MOS晶体管（T 2）和n掩埋层（120），以抑制源极（154）和漏极（156）之间的截止状态击穿。

公开(公告)号：US20070246773A1

公开(公告)日：2007-10-25

申请号：US11408692

申请日：2006-04-20

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1087 ,  H01L29/41 ,  H01L29/41725 ,  H01L29/42368 ,  H01L29/66659 ,  H03K19/00384

摘要： A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.

摘要翻译： 晶体管包括第一导电类型的源极区域并与第一半导体区域电连通。 晶体管还包括第一导电类型的漏极区域，并且与第一半导体区域不同的第二半导体区域电连通。 在第一半导体区域和第二半导体区域之间存在界面。 晶体管还包括电压抽头区域，该电压抽头区域至少包括位于比漏极区域更接近界面的位置的部分。 还描述了一种混合技术电路。

公开(公告)号：US20060124999A1

公开(公告)日：2006-06-15

申请号：US11012469

申请日：2004-12-15

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76

CPC分类号： H01L29/7816 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/66689

摘要： Semiconductor devices (102) and drain extended PMOS transistors (CT1a) are provided, as well as fabrication methods (202) therefor, in which a p-type separation region (130) is formed between an n-buried layer (108) and the transistor backgate (126) to increase breakdown voltage performance without increasing epitaxial thickness.

摘要翻译： 提供了半导体器件（102）和漏极延伸PMOS晶体管（CT1a）及其制造方法（202），其中p型分离区域（130）形成在n埋层（108） 和晶体管背栅（126），以增加击穿电压性能而不增加外延厚度。

公开(公告)号：US20060011974A1

公开(公告)日：2006-01-19

申请号：US10890648

申请日：2004-07-14

申请人： Sameer Pendharkar

发明人： Sameer Pendharkar

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/1083 ,  H01L27/0629 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7818

摘要： High side extended-drain MOS driver transistors (T2) are presented in which an extended drain (108, 156) is separated from a first buried layer (120) by a second buried layer (130), wherein an internal or external diode (148) is coupled between the first buried layer (120) and the extended drain (108, 156) to increase the breakdown voltage.

摘要翻译： 提出了高侧扩展漏极MOS驱动晶体管（T 2），其中扩展漏极（108,156）通过第二掩埋层（130）与第一掩埋层（120）分离，其中内部或外部二极管 148）耦合在第一掩埋层（120）和延伸漏极（108,156）之间以增加击穿电压。

公开(公告)号：US20050253191A1

公开(公告)日：2005-11-17

申请号：US10837918

申请日：2004-05-03

申请人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

发明人： Sameer Pendharkar ,  Ramanathan Ramani ,  Taylor Efland

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.

摘要翻译： 提供了扩大漏极MOS晶体管器件和制造方法，其中在第一导电类型的漏极和沟道之间形成第一导电类型的漂移区域。 所述漂移区域包括第一和第二部分，所述第一部分部分地在所述通道和所述第二部分之间的栅极结构下方延伸，并且所述第二部分在所述第一部分和所述漏极之间横向延伸，其中所述漂移区域的所述第一部分具有 第一种掺杂剂的浓度高于第二部分。

公开(公告)号：US06441431B1

公开(公告)日：2002-08-27

申请号：US09454934

申请日：1999-12-03

申请人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

发明人： Taylor Efland ,  Chin-Yu Tsai ,  Sameer Pendharkar

IPC分类号： H01L2976

CPC分类号： H01L29/66537 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7816 ,  H01L29/7833

摘要： An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well 204 of FIG. 1a) formed in the semiconductor substrate (layer 202 of FIG. 1a), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region 208 of FIG. 1a) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain 210 of FIG. 1a) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L1+L2), the drain region of the second conductivity type; a conductive gate electrode (layer 218 of FIG. 1a) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer 214 of FIG. 1a) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L1) and a first thickness; a second portion of the gate insulating layer which has a second length (L2) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

公开(公告)号：US08754497B2

公开(公告)日：2014-06-17

申请号：US12789040

申请日：2010-05-27

申请人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

发明人： Marie Denison ,  Seetharaman Sridhar ,  Sameer Pendharkar ,  Umamaheswari Aghoram

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7846

摘要： An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

摘要翻译： 在（100）衬底上的集成电路，其包含具有在<100>方向上取向的漂移区电流的n沟道扩展漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含n沟道延伸漏极MOS晶体管，其漂移区电流以<110>方向取向，在漂移区中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa压应力的应力元件。 （100）衬底上的集成电路，其包含具有沿着<110>方向取向的漂移区电流的p沟道延伸漏极MOS晶体管，并且在漂移区域中具有应力RESURF沟槽。 应力源RESURF沟槽具有超过100 MPa拉伸应力的应力元件。

公开(公告)号：US20130032922A1

公开(公告)日：2013-02-07

申请号：US13567456

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/266

摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

摘要翻译： 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US20130032863A1

公开(公告)日：2013-02-07

申请号：US13567340

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L27/07 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： An integrated circuit containing a gate controlled voltage divider having an upper resistor on field oxide in series with a transistor switch in series with a lower resistor. A resistor drift layer is disposed under the upper resistor, and the transistor switch includes a switch drift layer adjacent to the resistor drift layer, separated by a region which prevents breakdown between the drift layers. The switch drift layer provides an extended drain or collector for the transistor switch. A sense terminal of the voltage divider is coupled to a source or emitter node of the transistor and to the lower resistor. An input terminal is coupled to the upper resistor and the resistor drift layer. A process of forming the integrated circuit containing the gate controlled voltage divider.

摘要翻译： 一种集成电路，其包含栅极控制分压器，该栅极控制分压器具有与场效应晶体管上的上电阻串联的晶体管开关，与下电阻串联。 电阻器漂移层设置在上电阻器下方，并且晶体管开关包括与电阻器漂移层相邻的开关漂移层，由防止漂移层之间的击穿的区域分开。 开关漂移层为晶体管开关提供了扩展的漏极或集电极。 分压器的感测端子耦合到晶体管的源极或发射极节点和下电阻器。 输入端子耦合到上电阻器和电阻漂移层。 形成包含栅极控制分压器的集成电路的工艺。