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    Method and system to lower the minimum operating voltage of a memory array
    71.
    发明授权
    Method and system to lower the minimum operating voltage of a memory array 有权
    降低存储器阵列的最小工作电压的方法和系统

    公开(公告)号：US08094505B2

    公开(公告)日：2012-01-10

    申请号：US12576868

    申请日：2009-10-09

    申请人： Muhammad M. Khellah ,  Bibiche M. Geuskens ,  Arijit Raychowdhury

    发明人： Muhammad M. Khellah ,  Bibiche M. Geuskens ,  Arijit Raychowdhury

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/4085 ,  G11C5/145 ,  G11C11/4074 ,  G11C11/417

    摘要： A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.

    摘要翻译： 一种在存储器阵列的读取和/或写入操作期间降低存储器阵列的最小工作电压的方法和系统。 在本发明的一个实施例中，存储器阵列的读取和/或写入字线的电压在存储器阵列的读取和/或写入操作期间升高或增加。 通过这样做，存储器阵列中的NMOS器件被加强，并且在存储器阵列的读取和/或写入操作期间NMOS和PMOS器件之间的争用被减小。 这有助于在存储器阵列的读取和/或写入操作期间降低或减少存储器阵列所需的VCCmin。

    MEMORY ARRAY HAVING EXTENDED WRITE OPERATION
    72.
    发明申请
    MEMORY ARRAY HAVING EXTENDED WRITE OPERATION 审中-公开
    具有扩展写入操作的记忆阵列

    公开(公告)号：US20110149661A1

    公开(公告)日：2011-06-23

    申请号：US12642444

    申请日：2009-12-18

    申请人： Iqbal R. Rajwani ,  Satish K. Damaraju ,  Niranjan L. Cooray ,  Muhammad M. Khellah ,  Jaydeep P. Kulkarni

    发明人： Iqbal R. Rajwani ,  Satish K. Damaraju ,  Niranjan L. Cooray ,  Muhammad M. Khellah ,  Jaydeep P. Kulkarni

    IPC分类号： G11C7/00 ,  G11C8/08 ,  G11C8/18

    CPC分类号： G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C11/418

    摘要： In some embodiments, an apparatus comprising a memory array of static random access memory (SRAM) cells arranged in a plurality of rows and a plurality of columns and configured to receive a clock signal having a plurality of clock cycles; a plurality of word-lines associated with the plurality of rows of the SRAM cells; and a selected word-line driver configured during an extended write operation to drive a selected one of the plurality of word-lines with a write word-line signal having an extended duration. Other embodiments may be described and claimed.

    摘要翻译： 在一些实施例中，一种装置包括以多行排列并且被配置为接收具有多个时钟周期的时钟信号的静态随机存取存储器（SRAM）单元的存储器阵列; 与所述SRAM单元的所述多行相关联的多个字线; 以及在扩展写入操作期间配置的选择的字线驱动器，以用延长的持续时间的写入字线信号来驱动所述多个字线中的所选择的一个字线。 可以描述和要求保护其他实施例。

    Address hashing to help distribute accesses across portions of destructive read cache memory
    73.
    发明申请
    Address hashing to help distribute accesses across portions of destructive read cache memory 审中-公开
    地址散列可帮助分布访问破坏性读缓存内存的部分

    公开(公告)号：US20080162869A1

    公开(公告)日：2008-07-03

    申请号：US11648297

    申请日：2006-12-29

    申请人： Nam Sung Kim ,  Muhammad M. Khellah ,  Vivek De

    发明人： Nam Sung Kim ,  Muhammad M. Khellah ,  Vivek De

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0893 ,  G06F12/0864 ,  G11C2207/2245

    摘要： For one disclosed embodiment, an apparatus may comprise cache memory circuitry including multiple portions of destructive read memory cells and access control circuitry to access portions of destructive read memory cells. The apparatus may also comprise address hash logic to receive an address and to generate a hashed address based at least in part on at least a portion of the received address using a hashing technique to help distribute accesses by the access control circuitry across different portions of destructive read memory cells. Other embodiments are also disclosed.

    摘要翻译： 对于一个公开的实施例，装置可以包括高速缓存存储器电路，其包括破坏性读取存储器单元的多个部分和访问破坏性读取存储器单元的部分的访问控制电路。 该装置还可以包括地址散列逻辑以接收地址并且至少部分地基于所接收的地址的至少一部分使用散列技术来生成散列地址，以帮助分配访问控制电路在不同部分的破坏性的访问 读取存储单元。 还公开了其他实施例。

    Memory cell with improved write margin
    77.
    发明授权
    Memory cell with improved write margin 有权
    具有改善写入容限的存储单元

    公开(公告)号：US09111600B2

    公开(公告)日：2015-08-18

    申请号：US13997633

    申请日：2012-03-30

    申请人： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

    发明人： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

    IPC分类号： G11C7/00 ,  G11C5/14 ,  G11C11/413

    CPC分类号： G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

    摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

    摘要翻译： 描述了一种用于改善存储器单元中的写入裕度的装置和系统。 在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段 的脉冲信号。 在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

    METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY
    79.
    发明申请
    METHOD AND SYSTEM TO LOWER THE MINIMUM OPERATING VOLTAGE OF A MEMORY ARRAY 有权
    降低存储器阵列最小工作电压的方法和系统

    公开(公告)号：US20110085389A1

    公开(公告)日：2011-04-14

    申请号：US12576868

    申请日：2009-10-09

    申请人： Muhammad M. Khellah ,  Bibiche M. Geuskens ,  Arijit Raychowdhury

    发明人： Muhammad M. Khellah ,  Bibiche M. Geuskens ,  Arijit Raychowdhury

    IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C5/14

    CPC分类号： G11C11/4085 ,  G11C5/145 ,  G11C11/4074 ,  G11C11/417

    摘要： A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.

    摘要翻译： 一种在存储器阵列的读取和/或写入操作期间降低存储器阵列的最小工作电压的方法和系统。 在本发明的一个实施例中，存储器阵列的读取和/或写入字线的电压在存储器阵列的读取和/或写入操作期间升高或增加。 通过这样做，存储器阵列中的NMOS器件被加强，并且在存储器阵列的读取和/或写入操作期间NMOS和PMOS器件之间的争用被减小。 这有助于在存储器阵列的读取和/或写入操作期间降低或减少存储器阵列所需的VCCmin。