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    Thermal sensor device
    1.
    发明授权
    Thermal sensor device 有权
    热传感器装置

    公开(公告)号：US09121768B2

    公开(公告)日：2015-09-01

    申请号：US13328546

    申请日：2011-12-16

    Applicant: Arijit Raychowdhury ,  Hasnain Lakdawala ,  Yee (William) Li ,  Greg Taylor ,  Soumyanath Krishnamurthy

    Inventor： Arijit Raychowdhury ,  Hasnain Lakdawala ,  Yee (William) Li ,  Greg Taylor ,  Soumyanath Krishnamurthy

    IPC: G01K7/00 ,  G01K7/01

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.

    Abstract translation: 提供了一种热传感器，其包括前端部件，模数转换器和数字后端。 前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。 前端组件根据两个二极管的电流在两个输出节点提供模拟信号。 模数转换器从前端组件接收模拟信号并提供输出信号。 数字后端从模数转换器接收输出信号并提供计算温度。

    METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED MEMORY CELL BASED ON A PULSED READ CURRENT
    2.
    发明申请
    METHODS AND SYSTEMS TO READ A MAGNETIC TUNNEL JUNCTION (MTJ) BASED MEMORY CELL BASED ON A PULSED READ CURRENT 有权
    基于脉冲读取电流读取基于磁悬浮连接（MTJ）的存储单元的方法和系统

    公开(公告)号：US20150206564A1

    公开(公告)日：2015-07-23

    申请号：US14350997

    申请日：2012-03-25

    Applicant: Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

    Inventor： Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

    IPC: G11C11/16 ,  G11C5/12

    CPC classification number: G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

    Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

    Abstract translation: 基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。 对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列 在BL上。 可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。 预充电的BL电容也可以用作电压积分器。

    Multi-supply sequential logic unit
    3.
    发明授权
    Multi-supply sequential logic unit 有权
    多电源顺序逻辑单元

    公开(公告)号：US08901819B2

    公开(公告)日：2014-12-02

    申请号：US13992894

    申请日：2011-12-14

    Applicant: Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    Inventor： Arijit Raychowdhury ,  Jaydeep P. Kulkarni ,  James W. Tschanz

    IPC: H03K19/0175

    CPC classification number: H03K19/017509 ,  G06F1/10 ,  G06F1/3296 ,  Y02D10/172

    Abstract: Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

    Abstract translation: 这里描述了用于减少处理器中的顺序逻辑单元的时钟到输出延迟的装置，方法和系统。 所述装置包括顺序单元，包括：数据路径，用于接收输入信号，包括在第一电源电平上操作的逻辑门，所述数据路径以产生输出信号; 以及时钟路径，包括用于在第二电源电平上操作的逻辑门，所述时钟路径的逻辑门使用采样信号对所述输入信号进行采样以产生所述输出信号，其中所述第二电源电平高于所述第一电力 供应水平。 该装置改善（即减少）顺序单元的建立时间，并允许处理器以最小工作电压（Vmin）运行，而不降低顺序单元的性能。

    SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS
    4.
    发明申请
    SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS 有权
    用于可编程器件阵列的基于转子扭矩的记忆元件

    公开(公告)号：US20140035617A1

    公开(公告)日：2014-02-06

    申请号：US13997962

    申请日：2012-03-30

    Applicant: Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    Inventor： Arijit Raychowdhury ,  James W. Tschanz ,  Vivek De

    IPC: H03K19/177

    CPC classification number: H03K19/17728 ,  G11C11/16 ,  H03K19/177

    Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

    Abstract translation: 这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。 基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全 和可重构硬件架构。 由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。 除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。 通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

    THERMAL SENSOR DEVICE
    8.
    发明申请
    THERMAL SENSOR DEVICE 审中-公开
    热传感器装置

    公开(公告)号：US20120087390A1

    公开(公告)日：2012-04-12

    申请号：US13328546

    申请日：2011-12-16

    Applicant: Arijit RAYCHOWDHURY ,  Hasnain Lakdawala ,  Yee (William) Li ,  Greg Taylor ,  Soumyanath Krishnamurthy

    Inventor： Arijit RAYCHOWDHURY ,  Hasnain Lakdawala ,  Yee (William) Li ,  Greg Taylor ,  Soumyanath Krishnamurthy

    IPC: G01K7/01

    CPC classification number: G01K7/015 ,  G01K2219/00

    Abstract: A thermal sensor is provided that includes a front-end component, an analog-to-digital converter and a digital backend. The front-end component including an array of current sources, a dynamic element matching (DEM) device, an analog chopper and two diodes to sense temperatures on the die. The front-end component to provide analog signals at two output nodes based on currents through the two diodes. The analog-to-digital converter to receive the analog signals from the front-end component and to provide an output signal. The digital backend to receive the output signal from the analog-to-digital converter and to provide a calculated temperature.

    Abstract translation: 提供了一种热传感器，其包括前端部件，模数转换器和数字后端。 前端部件包括电流源阵列，动态元件匹配（DEM）器件，模拟斩波器和两个二极管，用于感测管芯上的温度。 前端组件根据两个二极管的电流在两个输出节点提供模拟信号。 模数转换器从前端组件接收模拟信号并提供输出信号。 数字后端从模数转换器接收输出信号并提供计算温度。

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