公开(公告)号：US08187939B2

公开(公告)日：2012-05-29

申请号：US12565611

申请日：2009-09-23

申请人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

发明人： Sung-Shan Tai ,  Hamza Yilmaz ,  Anup Bhalla ,  Hong Chang ,  John Chen

IPC分类号： H01L21/336 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/0869 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and a method for making a semiconductor device are disclosed. A trench mask may be applied to a semiconductor substrate, which is etched to form trenches with three different widths. A first conductive material is formed at the bottom of the trenches. A second conductive material is formed over the first conductive material. An insulator layer separates the first and second conductive materials. A first insulator layer is deposited on top of the trenches. A body layer is formed in a top portion of the substrate. A source is formed in the body layer. A second insulator layer is applied on top of the trenches and the source. A contact mask is applied on top of the second insulator layer. Source and gate contacts are formed through the second insulator layer. Source and gate metal are formed on top of the second insulator layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 可以将沟槽掩模施加到半导体衬底，其被蚀刻以形成具有三个不同宽度的沟槽。 第一导电材料形成在沟槽的底部。 在第一导电材料上形成第二导电材料。 绝缘体层分离第一和第二导电材料。 第一绝缘体层沉积在沟槽的顶部。 主体层形成在基板的顶部。 源体形成在体层中。 第二绝缘体层被施加在沟槽和源的顶部上。 接触掩模施加在第二绝缘体层的顶部。 源极和栅极触点通过第二绝缘体层形成。 源极和栅极金属形成在第二绝缘体层的顶部上。

公开(公告)号：US20120018793A1

公开(公告)日：2012-01-26

申请号：US13200869

申请日：2011-10-04

申请人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

发明人： Anup Bhalla ,  François Hébert ,  Sung-Shan Tai ,  Sik K. Lui

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.

摘要翻译： 本发明公开了一种半导体功率器件。 沟槽半导体功率器件包括从半导体衬底的顶表面开口的沟槽栅极，被包围在设置在衬底底表面上的漏区以上的顶表面附近的体区中的源极区围绕。 所述半导体功率器件还包括植入离子块，所述植入离子块设置在所述身体区域旁边的台面区域的上表面上，所述植入离子块具有基本上大于0.3微米的厚度，用于阻挡体注入离子和源离子进入台面区域 从而可以减少用于制造半导体功率器件的掩模。

公开(公告)号：US20110233667A1

公开(公告)日：2011-09-29

申请号：US12782573

申请日：2010-05-18

申请人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

发明人： Sung-Shan Tai ,  Sik Lui ,  Xiaobin Wang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device.

摘要翻译： 公开了半导体器件和制造方法。 该器件包括形成在位于半导体衬底的有源区域中的沟槽中的多个栅电极。 第一栅极流道形成在基板中并电连接到栅电极，其中第一栅极流道围绕有源区。 第二浇口浇道连接到第一浇口浇道并且位于活性区域和终止区域之间。 终端结构围绕第一和第二栅极流道和有源区域。 端接结构包括在衬底中的绝缘体衬里的沟槽中的导电材料，其中端接结构电气短路到衬底的源极或体层，从而形成用于器件的通道停止。

公开(公告)号：US20110092035A1

公开(公告)日：2011-04-21

申请号：US12928813

申请日：2010-12-20

申请人： YongZhong Hu ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Sung-Shan Tai

IPC分类号： H01L21/8242

CPC分类号： H01L27/0629 ,  H01L28/20 ,  H01L28/60 ,  Y10S438/957

摘要： A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

摘要翻译： 半导体器件包括晶体管，电容器和电阻器，其中电容器包括用作底部导电层的掺杂多晶硅层，其中具有作为顶部导电的Ti / TiN层覆盖的电介质层的硅化物块（SAB）层 从而构成单个多晶硅层金属 - 绝缘体 - 多晶硅（MIP）结构。 虽然高电阻rho电阻器也形成在同一个多晶硅层上，同时具有多晶硅层的差分掺杂。

公开(公告)号：US07829941B2

公开(公告)日：2010-11-09

申请号：US11338019

申请日：2006-01-24

申请人： Yongzhong Hu ,  Sung-Shan Tai

发明人： Yongzhong Hu ,  Sung-Shan Tai

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66734

摘要： A novel integration scheme for forming power MOSFET, particularly forming salicides for both gate and mesa contact regions, as well as using multiple energy contact implants through the salicided layer to form conductive body contacts which short to the source region by the salicides.

摘要翻译： 一种用于形成功率MOSFET的新型集成方案，特别是形成栅极和台面接触区域的杀螨剂，以及通过浸渍层使用多个能量接触植入物，以形成导电体接触物，其通过杀螨剂与源区域短接。

公开(公告)号：US20100105182A1

公开(公告)日：2010-04-29

申请号：US12655162

申请日：2009-12-22

申请人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

发明人： Sung-Shan Tai ,  Tiesheng Li ,  Anup Bhalla ,  Hong Chang ,  Moses Ho

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

摘要： Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening.

摘要翻译： 制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中通过硬掩模形成沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部 并且去除硬掩模以离开具有栅极顶表面的栅极，该栅极顶表面至少在沟槽开口的中心区域基本上在顶部衬底表面上方延伸，栅极具有包括延伸​​部分的垂直边缘，延伸部分 延伸到沟槽开口之上并与沟槽壁基本对齐。 它还包括植入物体，植入嵌入在体内的多个源区，形成多个间隔物，使得源极区域与栅极绝缘，多个间隔物紧邻栅极并且紧邻栅极 所述多个源极区域，其中所述多个间隔物基本上不延伸到所述沟槽中并且基本上不延伸穿过所述沟槽，在所述源极，所述间隔物，所述栅极以及所述主体的至少一部分之间设置介电层， 形成接触开口，并且在接触开口处设置金属以与身体形成接触。

公开(公告)号：US20100015770A1

公开(公告)日：2010-01-21

申请号：US12586257

申请日：2009-09-18

申请人： Sung-Shan Tai ,  Yongzhong Hu

发明人： Sung-Shan Tai ,  Yongzhong Hu

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： This invention discloses a method for manufacturing a trenched semiconductor power device that includes step of opening a trench in a semiconductor substrate. The method further includes a step of opening a top portion of the trench first then depositing a SiN on sidewalls of the top portion followed by etching a bottom surface of the top portion of the trench then silicon etching to open a bottom portion of the trench with a slightly smaller width than the top portion of the trench. The method further includes a step of growing a thick oxide layer along sidewalls of the bottom portion of the trench thus forming a bird-beak shaped layer at an interface point between the top portion and bottom portion of the trench.

摘要翻译： 本发明公开了一种制造沟槽半导体功率器件的方法，包括在半导体衬底中打开沟槽的步骤。 该方法还包括首先打开沟槽顶部的步骤，然后在顶部的侧壁上沉积SiN，随后蚀刻沟槽顶部的底部表面，然后进行硅蚀刻以打开沟槽的底部部分， 比沟槽的顶部稍小的宽度。 该方法还包括沿着沟槽底部的侧壁生长厚氧化物层的步骤，从而在沟槽的顶部和底部之间的界面处形成鸟嘴形层。

公开(公告)号：US07632733B2

公开(公告)日：2009-12-15

申请号：US11413248

申请日：2006-04-29

申请人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

发明人： Yu Wang ,  Tiesheng Li ,  Sung-Shan Tai ,  Hong Chang

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L22/12 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention discloses a semiconductor wafer for manufacturing electronic circuit thereon. The semiconductor substrate further includes an etch-back indicator that includes trenches of different sizes having polysilicon filled in the trenches and then completely removed from some of the trenches of greater planar trench dimensions and the polysilicon still remaining in a bottom portion in some of the trenches having smaller planar trench dimensions.

摘要翻译： 本发明公开了一种用于在其上制造电子电路的半导体晶片。 半导体衬底还包括回蚀指示器，其包括不同尺寸的沟槽，其具有填充在沟槽中的多晶硅，然后从更大的平面沟槽尺寸的一些沟槽中完全去除，并且多晶硅仍保留在一些沟槽中的底部 具有较小的平面沟槽尺寸。

公开(公告)号：US20090020854A1

公开(公告)日：2009-01-22

申请号：US11880455

申请日：2007-07-20

申请人： Tao Feng ,  Sung-Shan Tai

发明人： Tao Feng ,  Sung-Shan Tai

IPC分类号： H01L21/304 ,  B24B1/00

CPC分类号： H01L21/02035 ,  H01L21/02013 ,  H01L21/3043 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

摘要翻译： 公开了一种形成具有边缘支撑环的超薄晶片的工艺。 该工艺提供了具有与旋转蚀刻工艺兼容的成角度的内壁的边缘支撑环。

公开(公告)号：US20080237777A1

公开(公告)日：2008-10-02

申请号：US11729408

申请日：2007-03-27

申请人： YongZhong Hu ,  Sung-Shan Tai

发明人： YongZhong Hu ,  Sung-Shan Tai

IPC分类号： H01L29/00

CPC分类号： H01L29/7322 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/66689 ,  H01L29/7816

摘要： A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer.

摘要翻译： 半导体晶片包括至少部分制造的由高压低电压去耦层覆盖的高压晶体管和至少部分制造的低压晶体管，其中蚀刻掉高压低压去耦层， 电压制造工艺。 包括约30-150埃的高温氧化物（HTO）氧化物层和低压化学气相沉积（LPCVD）氮化物层的高压低电压去耦层。