公开(公告)号：US12182488B2

公开(公告)日：2024-12-31

申请号：US18362839

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

IPC: G06F30/392 ,  G06F30/337 ,  G06F30/394 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A device includes a power grid (PG) arrangement including: first and second segments in a first conductive layer which are conductive and extend in a first direction, the first segments being configured for a first reference voltage and the second segments being configured for a second reference voltage; the first and second segments being interspersed relative to a second direction, the second direction being perpendicular to the first direction; and relative to the second direction, the first segments being symmetrically spaced apart relative to each other, the second segments being symmetrically spaced apart relative to each other, and the second segments being substantially asymmetrically spaced between corresponding adjacent ones of the first segments.

公开(公告)号：US12112117B2

公开(公告)日：2024-10-08

申请号：US18308090

申请日：2023-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chung-Hsing Wang ,  Kuo-Nan Yang

IPC: G06F30/39 ,  G06F30/36 ,  G06F30/398 ,  H01L27/02 ,  H01L27/118

CPC classification number: G06F30/398 ,  G06F30/36 ,  G06F30/39 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: A method of manufacturing a semiconductor device includes forming a set of cells; forming a PG layer, including forming a first metallization layer including forming first conductor portions and second conductor portions, corresponding ones of the first conductor portions being arranged in first pairs; corresponding ones of the second conductor portions being arranged in second pairs; the cells being arranged to overlap at least one of the first and second conductor portions of the first metallization layer relative to the first direction; and forming a second metallization layer over the first metallization layer, the second metallization layer including forming third conductor portions and fourth conductor portions, the cells being arranged in a repeating relationship that each cell overlaps, an intersection of a corresponding one of the first or second pairs with at least a corresponding one of the third conductor portions or a corresponding one of the fourth conductor portions.

公开(公告)号：US11935833B2

公开(公告)日：2024-03-19

申请号：US17544937

申请日：2021-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hiranmay Biswas ,  Chi-Yeh Yu ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Stefan Rusu ,  Chin-Shen Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  G06F30/394

CPC classification number: H01L23/5286 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  G06F30/394

Abstract: A method of forming an IC structure includes forming first and second power rails at a power rail level. First metal segments are formed at a first metal level above the power rail level. Each first metal segment of the plurality of first metal segments overlap one or both of the first power rail or the second power rail. First vias are formed between the power rail level and the first metal level. Second metal segments are formed at a second metal level above the first metal level. At least one second metal segment of the plurality of second metal segments overlaps the first power rail. At least one second metal segment of the plurality of second metal segments overlaps the second power rail. A plurality of second vias are formed between the first metal level and the second metal level.

公开(公告)号：US11809803B2

公开(公告)日：2023-11-07

申请号：US17840887

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

CPC classification number: G06F30/398 ,  G06F30/394 ,  G06F30/367

Abstract: Failure-in-time (FIT) evaluation methods for an IC are provided. Data representing a layout of the IC is accessed, and the layout includes a metal line and a plurality of vertical interconnect accesses (VIAs). The metal line is divided into a first sub-line with a first line width and a second sub-line with a second line width. A plurality of nodes are picked along the first and second sub-lines of the metal line. The metal line is divided into a plurality of metal segments based on the nodes. FIT value is determined for each of the metal segments to verify the layout and fabricate the IC. The first line width is greater than the second line width.

公开(公告)号：US11756952B2

公开(公告)日：2023-09-12

申请号：US18066154

申请日：2022-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Kuang-Ching Chang ,  Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Kuo-Nan Yang

IPC: H01L27/02 ,  G06F1/3287

CPC classification number: H01L27/0207 ,  G06F1/3287

Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.

公开(公告)号：US11735625B2

公开(公告)日：2023-08-22

申请号：US17037438

申请日：2020-09-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chan Yang ,  Hui-Zhong Zhuang ,  Chih-Liang Chen ,  Ting-Wei Chiang ,  Cheng-I Huang ,  Kuo-Nan Yang

IPC: H01L29/06 ,  H01L27/092

CPC classification number: H01L29/0653 ,  H01L27/092

Abstract: A semiconductor device, including: a first OD strip, a first doping region, a second OD strip, a second doping region, and a third doping region. The first OD strip extending in a first direction is disposed on the first OD strip, and includes a first-type dopant to define an active region of a first MOS. The second OD strip extending in the first direction and immediately adjacent to the first OD strip in a second direction, wherein the second direction is orthogonal with the first direction. The second doping region is disposed on the second OD strip, and includes a second-type dopant to define an active region of a second MOS. The third doping region is disposed on the second OD strip, and includes the second-type dopant and is configured to be a body terminal of the first MOS.

公开(公告)号：US11669669B2

公开(公告)日：2023-06-06

申请号：US16943827

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Wan-Yu Lo ,  Shao-Huan Wang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Sheng-Hsiung Chen ,  Huang-Yu Chen

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/347 ,  H01L21/78

CPC classification number: G06F30/392 ,  G06F30/347 ,  H01L21/78

Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.

公开(公告)号：US20220384344A1

公开(公告)日：2022-12-01

申请号：US17332072

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Hsiung Chen ,  Jerry Chang Jui Kao ,  Kuo-Nan Yang ,  Jack Liu

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  G06F30/392 ,  G06F30/394

Abstract: An integrated circuit includes a device, a first interconnect structure disposed above the device and a second interconnect structure positioned below the device. The first interconnect structure includes multiple frontside metal layers. The second interconnect structure includes multiple backside metal layers, where each backside metal layer includes metal conductors routed according to diagonal routing. In some embodiments, a backside interconnect structure can include another backside metal layer that includes metal conductors routed according to mixed-Manhattan-diagonal routing. A variety of techniques can be used to route signals between metal conductors in the backside interconnect structure and cells on one or more frontside metal layers.

公开(公告)号：US11205032B2

公开(公告)日：2021-12-21

申请号：US16592200

申请日：2019-10-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Chung-Hsing Wang ,  Kuo-Nan Yang ,  Hiranmay Biswas

IPC: G06F30/392 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/398 ,  G06F119/06

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.

公开(公告)号：US10726174B2

公开(公告)日：2020-07-28

申请号：US15650131

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chin-Shen Lin ,  Meng-Xiang Lee ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/367 ,  G06F30/30 ,  G01R31/28 ,  G06F30/333 ,  G06F119/12

Abstract: A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.