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公开(公告)号：US20240153939A1
公开(公告)日：2024-05-09
申请号：US18410199
申请日：2024-01-11
发明人： Jack Liu
IPC分类号： H01L27/02 , G06F30/392 , H01L21/8234 , H01L23/528
CPC分类号： H01L27/0207 , G06F30/392 , H01L21/823475 , H01L23/5286 , G06F30/31
摘要： Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.
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公开(公告)号：US10510776B2
公开(公告)日：2019-12-17
申请号：US15939876
申请日：2018-03-29
发明人： Jack Liu , Jiann-Tyng Tzeng , Chih-Liang Chen , Chew-Yuen Young , Sing-Kai Huang , Ching-Fang Huang
IPC分类号： H01L27/12 , H01L21/761 , H01L21/84 , H01L21/762 , H01L29/10
摘要： A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.
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公开(公告)号：US09887863B2
公开(公告)日：2018-02-06
申请号：US14885352
申请日：2015-10-16
发明人： Huan-Neng Chen , William Wu Shen , Lan-Chou Cho , Feng Wei Kuo , Chewn-Pu Jou , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
CPC分类号： H04L27/0002 , H04B1/40 , H04B1/48 , H04B10/40 , H04L5/06 , H04L27/365 , H04L27/38 , H04L2027/0022
摘要： A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.
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公开(公告)号：US12095711B2
公开(公告)日：2024-09-17
申请号：US18190881
申请日：2023-03-27
发明人： Huan-Neng Chen , William Wu Shen , Chewn-Pu Jou , Feng Wei Kuo , Lan-Chou Cho , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
CPC分类号： H04L5/14 , H04W52/0261 , Y02D30/70
摘要： An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
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5.发明申请公开(公告)号：US20220068342A1
公开(公告)日：2022-03-03
申请号：US17524125
申请日：2021-11-11
发明人： Jack Liu , Charles Chew-Yuen Young
摘要： Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a data storage element; and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the data storage element. A delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The delay-sensing element is configured to sense a timing delay between a first signal on the active current path and a second signal on the reference current path. The delay-sensing element is further configured to determine a data state stored in the data storage element based on the timing delay.
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公开(公告)号：US11127626B2
公开(公告)日：2021-09-21
申请号：US17033759
申请日：2020-09-26
IPC分类号： H01L21/00 , H01L21/768 , H01L21/033 , H01L21/02
摘要： A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface is leveled with the first surface; and forming an alignment structure on the top surface. The method further includes forming a photoresist on the alignment layer to cover a portion of the top surface; and removing portions of the alignment layer uncovered by the photoresist to form an alignment structure on the top surface. The method further includes forming a dielectric surrounding the alignment structure on the first surface and over the alignment structure, removing a portion of the dielectric to expose the alignment structure by CMP; removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
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公开(公告)号：US10796947B2
公开(公告)日：2020-10-06
申请号：US16217469
申请日：2018-12-12
IPC分类号： H01L21/00 , H01L21/768 , H01L21/033 , H01L21/02
摘要： A method of manufacturing a semiconductor device includes providing a wafer having a first surface, wherein the wafer includes a gate electrode having a top surface, and the top surface of the gate electrode is substantially level with the first surface; and forming an alignment structure on the top surface of the gate electrode. The method further includes forming a dielectric surrounding the alignment structure on the first surface, removing the alignment structure to expose at least a portion of the top surface of the gate electrode, and forming a gate conductor over and in contact with the gate electrode.
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公开(公告)号：US12034076B2
公开(公告)日：2024-07-09
申请号：US17406884
申请日：2021-08-19
发明人： Chih-Liang Chen , Lei-Chun Chou , Jack Liu , Kam-Tou Sio , Hui-Ting Yang , Wei-Cheng Lin , Chun-Hung Liou , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8234 , H01L23/48 , H01L23/528 , H01L23/535 , H01L27/088 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/76871 , H01L21/823431 , H01L21/823475 , H01L23/481 , H01L23/528 , H01L23/5286 , H01L23/535 , H01L27/0886 , H01L29/66795 , H01L29/41791
摘要： A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.
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公开(公告)号：US11887978B2
公开(公告)日：2024-01-30
申请号：US17871005
申请日：2022-07-22
发明人： Jack Liu
IPC分类号： H01L29/417 , H01L29/20 , H01L27/02 , G06F30/392 , H01L21/8234 , H01L23/528 , G06F30/31 , G06F117/12
CPC分类号： H01L27/0207 , G06F30/392 , H01L21/823475 , H01L23/5286 , G06F30/31 , G06F2117/12
摘要： Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.
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公开(公告)号：US20220359492A1
公开(公告)日：2022-11-10
申请号：US17871005
申请日：2022-07-22
发明人： Jack Liu
IPC分类号： H01L27/02 , G06F30/392 , H01L21/8234 , H01L23/528
摘要： Disclosed embodiments herein relate to an integrated circuit including power switches with active regions connected to form a contiguous region. In one aspect, the integrated circuit includes a first layer including a first metal rail extending in a first direction. In one aspect, the integrated circuit includes a second layer above the first layer along a second direction perpendicular to the first direction. The second layer may include active regions for power switches. In one aspect, the active regions of the power switches are connected to form a contiguous region extending in the first direction. The first metal rail may be electrically coupled to the active regions through via contacts. In one aspect, the integrated circuit includes a third layer above the second layer along the second direction. The third layer may include a second metal rail electrically coupled to some of the power switches through additional via contacts.
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