公开(公告)号：US10658333B2

公开(公告)日：2020-05-19

申请号：US16199230

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

Abstract: A package structure includes at least one semiconductor die, an insulating encapsulant, an isolation layer and a redistribution layer. The at least one first semiconductor die has a semiconductor substrate and a conductive post disposed on the semiconductor substrate. The insulating encapsulant is partially encapsulating the first semiconductor die, wherein the conductive post has a first portion surrounded by the insulating encapsulant and a second portion that protrudes out from the insulating encapsulant. The isolation layer is disposed on the insulating encapsulant and surrounding the second portion of the conductive post. The redistribution layer is disposed on the first semiconductor die and the isolation layer, wherein the redistribution layer is electrically connected to the conductive post of the first semiconductor die.

公开(公告)号：US20200098731A1

公开(公告)日：2020-03-26

申请号：US16699098

申请日：2019-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The second die includes a plurality of through-substrate vias (TSVs). The metal circuit structure is disposed over a back side of the second die. The protective structure is sandwiched between and in contact with a bottom surface of the metal circuit structure and a top surface of one of the plurality of TSVs of the second die.

公开(公告)号：US20200051955A1

公开(公告)日：2020-02-13

申请号：US16655266

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzuan-Horng Liu ,  Hsien-Wei Chen ,  Jiun-Heng Wang ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/66 ,  H01L23/522

Abstract: A package structure includes a substrate, a first die, a second die and a bonding die. The substrate comprises scribe regions and die regions. The die regions are spaced from each other by the scribe regions therebetween. The first die and the second die are within the die regions of the substrate. The bonding die is electrically bonded to the first die and the second die. The top surfaces of the first die and the second die are partially covered by the bonding die.

公开(公告)号：US20190393194A1

公开(公告)日：2019-12-26

申请号：US16016670

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.

公开(公告)号：US20190355692A1

公开(公告)日：2019-11-21

申请号：US15983064

申请日：2018-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Feng Yeh ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/306 ,  H01L21/3105 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

Abstract: A 3DIC structure includes a die, a conductive terminal, and a dielectric structure. The die is bonded to a carrier through a bonding film. The conductive terminal is disposed over and electrically connected to the die. The dielectric structure comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is disposed laterally aside the die. The second dielectric layer is disposed between the first dielectric layer and the bonding film, and between the die and the boding film. A second edge of the second dielectric layer is more flat than a first edge of the first dielectric layer.

公开(公告)号：US20190096867A1

公开(公告)日：2019-03-28

申请号：US15717920

申请日：2017-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Hsien-Wei Chen ,  Sung-Feng Yeh ,  Chi-Hwang Tai

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L25/18

Abstract: A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The at least one semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the at least one semiconductor device and adheres the at least one semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the at least one semiconductor device, wherein the at least one semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the at least one semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.

公开(公告)号：US20170053844A1

公开(公告)日：2017-02-23

申请号：US14830740

申请日：2015-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ching Tsai ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/82 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/538 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/08235 ,  H01L2924/37001

Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.

Abstract translation: 提供了一种三维集成电路结构，其包括第一裸片，直通衬底通孔和连接器。 第一裸片与第一裸片的第一电介质层和第二裸片的第二电介质层结合到第二裸片，其中第一钝化层位于第一电介质层与第一裸片的第一衬底之间， 第一测试垫被嵌入在第一钝化层中。 穿通基板通孔穿过第一管芯并与第二管芯电连接。 连接器通过贯通基板通孔电连接到第一管芯和第二管芯。

公开(公告)号：US20250157876A1

公开(公告)日：2025-05-15

申请号：US19021576

申请日：2025-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen

IPC: H01L23/367 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

公开(公告)号：US20250044530A1

公开(公告)日：2025-02-06

申请号：US18526920

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chih-Tsung Tsai ,  Kuo Chin Hsu

IPC: G02B6/42

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized with an optical interposer. In embodiments a method patterns a substrate to form a recess with a sidewall, forms a mirror coating on the sidewall, deposits and patterns a material to form a first waveguide adjacent to the mirror coating, and bonds an optical interposer over the first waveguide.

公开(公告)号：US20240395751A1

公开(公告)日：2024-11-28

申请号：US18788526

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package includes a redistribution structure, a first device and a second device attached to the redistribution structure, the first device including: a first die, a support substrate bonded to a first surface of the first die, and a second die bonded to a second surface of the first die opposite the first surface, where a total height of the first die and the second die is less than a first height of the second device, and where a top surface of the substrate is at least as high as a top surface of the second device, and an encapsulant over the redistribution structure and surrounding the first device and the second device.