公开(公告)号：US11315855B2

公开(公告)日：2022-04-26

申请号：US16836926

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00

Abstract: Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

公开(公告)号：US20210313254A1

公开(公告)日：2021-10-07

申请号：US16836926

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/498

Abstract: Provided is a package structure including a photonic die, an electronic die, a conductive layer, a circuit substrate, and an underfill. The electronic die is bonded on a front side of the photonic die. The conductive layer is disposed on a back side of the photonic die. The conductive layer includes a plurality of conductive pads and a dam structure between the conductive pads and a first sidewall of the photonic die. The circuit substrate is bonded on the back side of the photonic die through a plurality of connectors and the conductive pads. The underfill laterally encapsulates the connectors, the conductive pads, and the dam structure. The underfill at the first sidewall of the photonic die has a first height, the underfill at a second sidewall of the photonic die has a second height, and the first height is lower than the second height.

公开(公告)号：US20210305209A1

公开(公告)日：2021-09-30

申请号：US16831776

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a first semiconductor die, a second semiconductor die, an insulating layer, and a first dual-damascene connector electrically connected to the first semiconductor die. The first semiconductor die includes a first bonding surface including a die attaching region and a peripheral region connected to the die attaching region. The second semiconductor die is electrically connected to the first semiconductor die, and a second bonding surface of the second semiconductor die is bonded to the first bonding surface in the die attaching region. The insulating layer disposed on the first bonding surface in the peripheral region extends along sidewalls of the second semiconductor die. The first dual-damascene connector includes a first portion disposed on the insulating layer, and a second portion penetrating through the insulating layer and landing on the first bonding surface in the peripheral region.

公开(公告)号：US20210134685A1

公开(公告)日：2021-05-06

申请号：US16919073

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Ying-Ju Chen

IPC: H01L21/66 ,  H01L21/78 ,  H01L23/10 ,  H01L23/00

Abstract: A method includes the following steps. A semiconductor wafer including integrated circuit components, seal rings respectively encircling the integrated circuit components and testing structures disposed between the seal rings is provided. A first wafer saw process is performed at least along a first path to singulate the semiconductor wafer into a plurality of first singulated integrated circuit components each including a testing structure among the testing structures. When performing the first wafer saw process, testing pads of the testing structures are located beside the first path, such that a testing pad of a corresponding one of the testing structures in the first singulated integrated circuit component is laterally spaced apart from a sidewall of the first singulated integrated circuit component by a distance.

公开(公告)号：US10797001B2

公开(公告)日：2020-10-06

申请号：US16601588

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/544 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

公开(公告)号：US20200251439A1

公开(公告)日：2020-08-06

申请号：US16852565

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00

Abstract: A semiconductor structure including a plurality of semiconductor dies, an insulating encapsulant, and a redistribution structure disposed on the semiconductor dies and the insulating encapsulant is provided. The insulating encapsulant is interposed between adjacent two of the semiconductor dies, and the insulating encapsulant includes a first portion wider than a second portion connected to the first portion. The redistribution structure includes a dielectric layer overlying the insulating encapsulant, and a conductive trace overlying the dielectric layer and opposite to the insulating encapsulant. The conductive trace includes at least one turn and is connected to a conductive terminal of one of the adjacent two of the semiconductor dies, and the conductive trace extends across the dielectric layer to reach another conductive terminal of another one of the adjacent two of the semiconductor dies.

公开(公告)号：US20190164925A1

公开(公告)日：2019-05-30

申请号：US16246564

申请日：2019-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00

Abstract: A semiconductor structure including an insulating encapsulant, a plurality of semiconductor dies separately embedded in the insulating encapsulant, and an electrical communication path is provided. The electrical communication path includes at least one turning wiring connected to a conductive terminal of one of the semiconductor dies and extending across and above the insulating encapsulant to reach another conductive terminal of another one of the semiconductor dies. A layout area of the at least one turning wiring is within a region corresponding to an edge of one of the semiconductor dies and a closest edge of the adjacent one of the semiconductor dies.

公开(公告)号：US09831215B1

公开(公告)日：2017-11-28

申请号：US15227865

申请日：2016-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Wei Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Wei-Yu Chen ,  Ying-Ju Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/562 ,  H01L25/50 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06582

Abstract: A semiconductor package includes at least one first semiconductor device, a first molding compound, a dielectric layer, at least one conductive feature and at least one compensating structure. The first molding compound is present on at least one sidewall of the first semiconductor device. The dielectric layer is present on the first molding compound and the first semiconductor device. The conductive feature present is at least partially in the dielectric layer and electrically connected to the first semiconductor device. The compensating structure is present at least partially in the dielectric layer. The compensating structure is monolithically connected to the first molding compound.

公开(公告)号：US09825008B1

公开(公告)日：2017-11-21

申请号：US15227870

申请日：2016-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Ju Chen ,  Jie Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/02 ,  H01L23/22 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L22/20 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/15311

Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.