公开(公告)号：US10784168B2

公开(公告)日：2020-09-22

申请号：US16154035

申请日：2018-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui-Ting Yang ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Meng-Hung Shen ,  Ru-Gun Liu ,  Wei-Cheng Lin

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.

公开(公告)号：US10727113B2

公开(公告)日：2020-07-28

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/33 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3105

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US10707081B2

公开(公告)日：2020-07-07

申请号：US16178417

申请日：2018-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US10678142B2

公开(公告)日：2020-06-09

申请号：US16057277

申请日：2018-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Dong-Yo Jheng ,  Ken-Hsien Hsieh ,  Shih-Ming Chang ,  Chih-Jie Lee ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/36

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

公开(公告)号：US20200152464A1

公开(公告)日：2020-05-14

申请号：US16725731

申请日：2019-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yuan Tseng ,  Wei-Liang Lin ,  Li-Te Lin ,  Ru-Gun Liu ,  Min Cao

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/417

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a mandrel over a substrate, the mandrel having a first sidewall and a second sidewall opposing the first sidewall; forming a first fin on the first sidewall and a second fin on the second sidewall; depositing a dielectric material covering the first fin, the second fin, and the mandrel; partially removing the dielectric material, thereby exposing the second fin; etching the second fin without etching the first fin and the mandrel; removing the dielectric material; and removing the mandrel.

公开(公告)号：US10417376B2

公开(公告)日：2019-09-17

申请号：US15997513

申请日：2018-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsu-Ting Huang ,  Shuo-Yen Chou ,  Ru-Gun Liu

IPC: G06F17/50 ,  G03F1/78 ,  G03F1/70

Abstract: Source beam optimization (SBO) methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an integrated circuit (IC) design layout and performing an SBO process using the IC design layout to generate a mask shot map and an illumination source map. The SBO process uses an SBO model that collectively simulates a mask making process using the mask shot map and a wafer making process using the illumination source map. A mask can be fabricated using the mask shot map, and a wafer can be fabricated using the illumination source map (and, in some implementations, using the mask fabricated using the mask shot map). The wafer includes a final wafer pattern that corresponds with a target wafer pattern defined by the IC design layout. The SBO methods disclosed herein can significantly reduce (or eliminate) variances between the final wafer pattern and the target wafer pattern.

公开(公告)号：US10354874B2

公开(公告)日：2019-07-16

申请号：US15812750

申请日：2017-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chun Huang ,  Chin-Hsiang Lin ,  Chien-Wen Lai ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

公开(公告)号：US20190122987A1

公开(公告)日：2019-04-25

申请号：US16216075

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Charles Chew-Yuen Young ,  Chi-Yeh Yu ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Pin-Dai Sue ,  Ru-Gun Liu ,  Shih-Wei Peng ,  Wen-Hao Chen ,  Yung-Sung Yen ,  Chun-Kuang Chen

IPC: H01L23/528 ,  H01L27/12 ,  H01L27/088 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/092 ,  H01L23/522 ,  H01L21/8238

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a source region and a drain region separated by a channel region within a substrate. A middle-end-of-the-line (MEOL) structure is over the drain region and a gate structure is over the channel region. The MEOL structure is vertically disposed between the drain region and a plane extending along an upper surface of the gate structure. A first interconnect wire is connected to the MEOL structure by a first conductive contact that is directly over the drain region and that extends between the first interconnect wire and the MEOL structure. A conductive strap is located over the first interconnect wire. The conductive strap connects the first interconnect wire to a power rail having a larger width than the first interconnect wire.

公开(公告)号：US20190080921A1

公开(公告)日：2019-03-14

申请号：US15704367

申请日：2017-09-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Wen-Li Cheng ,  Dong-Yo Jheng ,  Chih-Ming Lai ,  Ru-Gun Liu

IPC: H01L21/308 ,  G06F17/50

Abstract: A method of fabricating an integrated circuit (IC) with first and second different lithography techniques includes providing a layout of the IC having IC patterns; and deriving a graph from the layout. The graph has vertices and edges connecting some of the vertices. The vertices represent the IC patterns. The edges are classified into at least two types, a first type connecting two vertices that are to be patterned separately with the first and second lithography techniques, a second type connecting two vertices that are to be patterned in a same process using the first lithography technique or to be patterned separately with the first and second lithography techniques. The method further includes decomposing the vertices into first and second subsets, wherein the IC patterns corresponding to the first and second subsets are to be patterned on a wafer using the first and second lithography techniques respectively.

公开(公告)号：US20190042685A1

公开(公告)日：2019-02-07

申请号：US16133110

申请日：2018-09-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ken-Hsien Hsieh ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Wen-Chun Huang ,  Wen-Li Cheng ,  Pai-Wei Wang

IPC: G06F17/50 ,  G03F1/70 ,  G03F1/36

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.