公开(公告)号：US08553444B2

公开(公告)日：2013-10-08

申请号：US12743472

申请日：2009-08-20

申请人： Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

发明人： Shunsaku Muraoka ,  Yoshihiko Kanzawa ,  Satoru Mitani ,  Koji Katayama ,  Kazuhiko Shimakawa ,  Satoru Fujii ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： H01L45/147 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

摘要： A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOX and MOy (where x

摘要翻译： 一种可变电阻非易失性存储装置，包括：（i）半导体衬底（301），（ii）具有下电极和上电极（309a，309c）的可变电阻元件（309） 和可变电阻层（309b），其电阻值基于各自具有不同极性的电压信号而被可逆地变化并施加在电极（309a，309c）之间，以及（iii）形成在基板上的MOS晶体管 （301），其中所述可变电阻层（309b）包括：具有组成MOX和MOy（其中x

公开(公告)号：US08445885B2

公开(公告)日：2013-05-21

申请号：US13132058

申请日：2009-12-01

申请人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

发明人： Yoshihiko Kanzawa ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

IPC分类号： H01L29/02

CPC分类号： H01L27/101 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element includes first and second electrodes, and a resistance variable layer disposed therebetween. At least one of the first and second electrodes includes a platinum-containing layer. The resistance variable layer includes a first oxygen-deficient transition metal oxide layer which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer. When oxygen-deficient transition metal oxides included in the first and second oxygen-deficient transition metal oxide layers are expressed as MOx, and MOy, respectively, x

摘要翻译： 非易失性存储元件包括第一和第二电极以及设置在它们之间的电阻变化层。 第一和第二电极中的至少一个包括含铂层。 电阻变化层包括不与含铂层物理接触的第一缺氧过渡金属氧化物层和设置在第一缺氧过渡金属氧化物层和第二缺氧过渡金属氧化物层之间的第二缺氧过渡金属氧化物层 所述含铂层并且与所述含铂层物理接触。 包含在第一和第二缺氧过渡金属氧化物层中的缺氧过渡金属氧化物分别表示为MOx，MOy分别表示为x

公开(公告)号：US08405076B2

公开(公告)日：2013-03-26

申请号：US12920154

申请日：2010-02-03

申请人： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

发明人： Takeki Ninomiya ,  Takeshi Takagi ,  Zhiqiang Wei

IPC分类号： H01L29/12

CPC分类号： H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1625 ,  H01L45/1675

摘要： A nonvolatile memory element (100) includes a variable resistance layer (107) including a first metal oxide MOx and a second metal oxide MOy, and reaction energy of chemical reaction related to the first metal oxide, the second metal oxide, oxygen ions, and electrons is 2 eV or less. The chemical reaction is expressed by a formula 13, where a combination (MOx, MOy) of MOx and MOy is selected from a group including (Cr2O3, CrO3), (Co3O4, Co2O3), (Mn3O4, Mn2O3), (VO2, V2O5), (Ce2O3, CeO2), (W3O8, WO3), (Cu2O, CuO), (SnO, SnO2), (NbO2, Nb2O5), and (Ti2O3, TiO2). [Mathematical Expression 13] MOx+(y−x)O2−MOy+2(y−x)e−  (Formula 13)

摘要翻译： 非易失性存储元件（100）包括可变电阻层（107），其包括第一金属氧化物MOx和第二金属氧化物MOy，以及与第一金属氧化物，第二金属氧化物，氧离子和 电子为2eV以下。 化学反应由式13表示，其中MOx和MOy的组合（MOx，MOy）选自（Cr 2 O 3，CrO 3），（Co 3 O 4，Co 2 O 3），（Mn 3 O 4，Mn 2 O 3），（VO 2，V 2 O 5） ），（Ce 2 O 3，CeO 2），（W3O 8，WO 3），（Cu 2 O，CuO），（SnO，SnO 2），（NbO 2，Nb 2 O 5）和（Ti 2 O 3，TiO 2）。 [数学表达式13] MOx +（y-x）O2-MOy + 2（y-x）e-（式13）

公开(公告)号：US08338816B2

公开(公告)日：2012-12-25

申请号：US12682676

申请日：2008-03-31

申请人： Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

发明人： Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Satoru Mitani ,  Zhiqiang Wei ,  Takeshi Takagi

IPC分类号： H01L47/00 ,  H01L29/02 ,  H01L29/66

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625

摘要： A nonvolatile memory element of the present invention comprises a first electrode (503); a second electrode (505); and a resistance variable layer (504) which is disposed between the first electrode (503) and the second electrode (505), a resistance value of the resistance variable layer being changeable in response to electric signals which are applied between the first electrode (503) and the second electrode (505), wherein the first electrode and the second electrode comprise materials which are made of different elements.

摘要翻译： 本发明的非易失性存储元件包括第一电极（503）; 第二电极（505）; 以及设置在第一电极（503）和第二电极（505）之间的电阻变化层（504），电阻变化层的电阻值根据施加在第一电极（503）和第二电极 ）和第二电极（505），其中第一电极和第二电极包括由不同元件制成的材料。

公开(公告)号：US20120280199A1

公开(公告)日：2012-11-08

申请号：US13512178

申请日：2010-11-18

申请人： Takeshi Takagi

发明人： Takeshi Takagi

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1683

摘要： Provided is a nonvolatile memory element achieving a stable resistance change and miniaturization, and a method of manufacturing the same. The nonvolatile memory element includes: a first electrode formed above a substrate; an interlayer insulating layer formed above the substrate including the first electrode and having a memory cell hole reaching the first electrode; a barrier layer formed in the memory cell hole and composed of a semiconductor layer or an insulating layer connected to the first electrode; a second electrode formed in the memory cell hole and connected to the barrier layer; a variable resistance layer formed on the second electrode and having a stacked structure whose resistance value changes based on electric signals; and a third electrode connected to the variable resistance layer and formed on the interlayer insulating layer to cover the memory cell hole.

摘要翻译： 提供了实现稳定的电阻变化和小型化的非易失性存储元件及其制造方法。 非易失性存储元件包括：形成在衬底上的第一电极; 形成在包括所述第一电极并且具有到达所述第一电极的存储单元孔的所述基板的上方的层间绝缘层; 由存储单元孔形成的阻挡层，由与第一电极连接的半导体层或绝缘层构成; 形成在所述存储单元孔中并连接到所述阻挡层的第二电极; 形成在所述第二电极上并具有电阻值基于电信号而变化的堆叠结构的可变电阻层; 以及连接到所述可变电阻层并形成在所述层间绝缘层上以覆盖所述存储单元孔的第三电极。

公开(公告)号：US08179714B2

公开(公告)日：2012-05-15

申请号：US12865193

申请日：2009-10-16

申请人： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

发明人： Takeshi Takagi ,  Shunsaku Muraoka ,  Mitsuteru Iijima ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

摘要： Provided is a nonvolatile storage device (200) capable of stably operating without increasing a size of a selection transistor included in each of memory cells. The nonvolatile storage device (200) includes: a semiconductor substrate (301) which has a P-type well (301a) of a first conductivity type; a memory cell array (202) which includes memory cells (M11) or the like each of which includes a variable resistance element (R11) and a transistor (N11) that are formed above the semiconductor substrate (301) and connected in series; and a substrate bias circuit (220) which applies, to the P-type well (301a), a bias voltage in a forward direction with respect to a source and a drain of the transistor (N11), when a voltage pulse for writing is applied to the variable resistance element (R11) included in the selected memory cell (M11) or the like.

摘要翻译： 提供一种能够在不增加包含在每个存储单元中的选择晶体管的尺寸的情况下稳定地工作的非易失性存储装置（200）。 非易失性存储装置（200）包括：具有第一导电型的P型阱（301a）的半导体基板（301） 存储单元阵列（202），其包括存储单元（M11）等，每个存储单元包括形成在半导体衬底（301）上并串联连接的可变电阻元件（R11）和晶体管（N11）; 以及衬底偏置电路（220），当用于写入的电压脉冲为写入电压脉冲时，向P型阱（301a）施加相对于晶体管（N11）的源极和漏极的正向偏置电压 应用于所选择的存储单元（M11）等中包含的可变电阻元件（R11）。

公开(公告)号：US20120104351A1

公开(公告)日：2012-05-03

申请号：US13382321

申请日：2011-06-29

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： H01L45/00

CPC分类号： H01L27/2409 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/249 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1633

摘要： A stacking structure in which a stacked body (21) including a first conductive layer (13), a semiconductor layer (17), and a second conductive layer (18) and an interlayer insulating film (16) are alternately stacked in parallel to a substrate, a plurality of columnar electrodes (12) arranged so as to penetrated through the stacking structure in a stacking direction, a variable resistance layer (14) which is disposed between the columnar electrode (12) and the first conductive layer (13) and which has a resistance value that reversibly changes according to an application of an electric signal are included. The variable resistance layer (14) is formed by oxidizing part of the first conductive layer (13). The variable resistance layer (14) and an insulating film for electrically separating the semiconductor layer (17) and the second conductive layer (18) from the columnar electrode (12) are simultaneously formed in a single oxidation process.

摘要翻译： 层叠结构，其中包括第一导电层（13），半导体层（17）和第二导电层（18）和层间绝缘膜（16）的层叠体（21）与 基板，多个柱状电极（12），被布置成沿堆叠方向穿过堆叠结构，设置在柱状电极（12）和第一导电层（13）之间的可变电阻层（14）和 其具有根据电信号的应用可逆地改变的电阻值。 可变电阻层（14）通过氧化第一导电层（13）的一部分而形成。 在单次氧化过程中同时形成可变电阻层（14）和用于将半导体层（17）和第二导电层（18）与柱状电极（12）电分离的绝缘膜。

公开(公告)号：US20110299322A1

公开(公告)日：2011-12-08

申请号：US13201890

申请日：2011-02-01

申请人： Mitsuteru Iijima ,  Takeshi Takagi

发明人： Mitsuteru Iijima ,  Takeshi Takagi

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/146

摘要： A method of programming a variable resistance element includes: performing a writing step by applying a writing voltage pulse having a first polarity to a transition metal oxide comprising two metal oxide layers which are stacked, so as to change a resistance state of the transition metal oxide from high to low, each of the two metal oxide layers having a different degree of oxygen deficiency; and performing an erasing step by applying an erasing voltage pulse having a second polarity to the transition metal oxide so as to change the resistance state of the transition metal oxide from low to high, the second polarity being different from the first polarity, wherein |Vw1|>|Vw2| is satisfied, where Vw1 represents a voltage value of the writing voltage pulse for first to N-th writing steps, and Vw2 represents a voltage value of the writing voltage pulse for (N+1)-th and subsequent writing steps, where N is equal to or more than 1, te1>te2 is satisfied, where te1 represents a pulse width of the erasing voltage pulse for first to M-th erasing steps, and te2 represents a pulse width of the erasing voltage pulse for (M+1)-th and subsequent erasing steps, where M is equal to or more than 1, and the (N+1)-th writing step follows the M-th erasing step.

摘要翻译： 编程可变电阻元件的方法包括：通过将包含第一极性的写入电压脉冲施加到包含堆叠的两个金属氧化物层的过渡金属氧化物来进行写入步骤，以改变过渡金属氧化物的电阻状态 从高到低，两个金属氧化物层中的每一个具有不同程度的氧气缺乏; 以及通过向所述过渡金属氧化物施加具有第二极性的擦除电压脉冲以便将所述过渡金属氧化物的电阻状态从低变为高而进行擦除步骤，所述第二极性与所述第一极性不同，其中| Vw1 |> | Vw2 | 其中Vw1表示第一至第N写入步骤的写入电压脉冲的电压值，Vw2表示第（N + 1）个和后续写入步骤的写入电压脉冲的电压值，其中N是 等于或大于1，则te1> te2被满足，其中te1表示用于第一至第M擦除步骤的擦除电压脉冲的脉冲宽度，te2表示（M + 1）个擦除电压脉冲的脉冲宽度， 其中M等于或大于1，并且第（N + 1）个写入步骤在第M擦除步骤之后。

公开(公告)号：US20110075469A1

公开(公告)日：2011-03-31

申请号：US12993706

申请日：2010-03-15

申请人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

发明人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

摘要翻译： 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。

公开(公告)号：US07916516B2

公开(公告)日：2011-03-29

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。