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    Processor for processing data string by byte-by-byte
    71.
    发明授权
    Processor for processing data string by byte-by-byte 失效
    用于逐字节处理数据字符串的处理器

    公开(公告)号：US5465374A

    公开(公告)日：1995-11-07

    申请号：US3369

    申请日：1993-01-12

    申请人： Robert M. Dinkjian ,  Lisa C. Heller ,  Steven R. Kordus ,  Kenneth A. Lauricella ,  Thomas W. Seigendall ,  Robert A. Skaggs ,  Nelson S. Xu

    发明人： Robert M. Dinkjian ,  Lisa C. Heller ,  Steven R. Kordus ,  Kenneth A. Lauricella ,  Thomas W. Seigendall ,  Robert A. Skaggs ,  Nelson S. Xu

    IPC分类号： G06F7/02 ,  G06F7/74 ,  G06F9/308 ,  G06F7/00

    CPC分类号： G06F7/74 ,  G06F7/026 ,  G06F9/30018

    摘要： A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string. The offset is used to shift the byte count mask by a number of positions corresponding to the position of the first byte of the string and inserts 0s in the byte count mask for positions not belonging to the string. A byte-by-byte comparator determines string end conditions and provides an output word with a significant bit indication for each byte for which an end condition has been detected. The output of the byte-by-byte comparator is combined with the shifted byte count mask, and the result is decoded by means of a prioritized decoder which generates a string write mask.

    摘要翻译： 数据处理器处理来自存储器的数据串，其中数据串不开始或在存储器边界处结束。 字符串在存储器中由起始地址定义，定义字符串总字节数的字节数以及定义起始地址位置中第一个字节的位置的字节偏移量。 处理器存储字节计数，并在处理每个多字节字时减少字节计数。 字节计数掩码电路产生一个字节计数掩码，每个字节计数的字节数大于每个存储字的字节数。 当待处理的剩余字节数低于存储器字中的字节数时，字节计数掩码仅针对与最后一个存储器字中字符串的字节位置相对应的位置产生1。 偏移寄存器存储定义字符串的第一个存储字中第一个字节的位置的偏移量。 偏移用于将字节计数掩码移位与字符串的第一个字节的位置相对应的位置数，并将不属于字符串的位置插入到字节计数掩码中的0。 逐字节比较器确定字符串结束条件，并为已经检测到结束条件的每个字节提供具有有效位指示的输出字。 逐字节比较器的输出与移位的字节计数掩码组合，结果通过生成字符串写入掩码的优先级解码器解码。

    Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field
    75.
    发明申请
    Load Page Table Entry Address Instruction Execution Based on an Address Translation Format Control Field 有权
    基于地址转换格式控制字段加载页表输入地址指令执行

    公开(公告)号：US20120011341A1

    公开(公告)日：2012-01-12

    申请号：US13234374

    申请日：2011-09-16

    申请人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： Dan F. Greiner ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1009 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

    摘要翻译： 提供了为计算机系统的机器结构定义的加载页表项地址函数。 在一个实施例中，获得机器指令，其中包含指示要执行加载页表项地址函数的操作码。 机器指令包含M字段，标识第一通用寄存器的第一字段和标识第二通用寄存器的第二字段。 基于M场的内容，获得具有至少一个分段表的地址转换表的层次结构的初始起始地址。 基于获得的初始起始地址，执行动态地址转换，直到获得页表项。 页表入口地址保存在识别的第一个通用寄存器中。

    DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER
    77.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH TRANSLATION EXCEPTION QUALIFIER 有权
    动态地址翻译与翻译例外的合格者

    公开(公告)号：US20090216992A1

    公开(公告)日：2009-08-27

    申请号：US12037268

    申请日：2008-02-26

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0284 ,  G06F3/0604 ,  G06F3/0667 ,  G06F3/067 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/109 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/657

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的动态地址转换进行。 响应于在动态地址转换期间发生的翻译中断，比特被存储在转换异常限定符（TXQ）字段中，以指示异常是在运行主机程序或主机DAT异常发生时发生的主机DAT异常 同时运行一个客人程序。 TXQ还能够指示异常与从访客页面帧实际地址或访客段帧绝对地址导出的主机虚拟地址相关联。 TXQ还能够指示较大或较小的主机帧大小优于后端客机帧。

    DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL
    78.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH ACCESS CONTROL 有权
    动态地址翻译与访问控制

    公开(公告)号：US20090182974A1

    公开(公告)日：2009-07-16

    申请号：US11972682

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles E. Webb

    发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles E. Webb

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1475 ,  G06F12/1036 ,  G06F12/109

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 基于原始地址，获得包含格式控制字段和访问有效性字段的段表条目。 如果启用格式控制和访问有效性，则段表条目还包含访问控制和提取保护字段以及段帧绝对地址。 仅当访问控制字段与由程序状态字或正在执行的程序指令的操作数提供的程序访问键匹配时，才允许对数据块进行存储操作。 只有当与虚拟地址相关联的程序访问密钥等于段访问控制字段时，才允许从所需数据块获取操作。

    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT
    79.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FRAME MANAGEMENT 有权
    动态地址翻译与框架管理

    公开(公告)号：US20090182966A1

    公开(公告)日：2009-07-16

    申请号：US11972713

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    发明人： DAN F. GREINER ,  Charles W. Gainey, JR. ,  Lisa C. Heller ,  Damian L. Osisek ,  Timothy J. Slegel ,  Gustav E. Sittmann

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1475 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30145 ,  G06F12/00 ,  G06F12/023 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/68

    摘要： What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.

    摘要翻译： 公开的是针对计算机系统的机器结构定义的帧管理功能。 在一个实施例中，获得识别第一和第二通用寄存器的帧管理指令。 第一通用寄存器包含具有带有访问保护位的密钥字段和块大小指示的帧管理字段。 如果块大小指示指示大块，则从第二通用寄存器获得大数据块的操作数地址。 大块数据具有多个小块，每个小块与具有多个存储密钥访问保护位的对应存储密钥相关联。 如果块大小指示指示大块，则使用密钥字段的访问保护位来设置大块内的每个小块的每个相应的存储密钥的存储密钥访问保护位。

    DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL
    80.
    发明申请
    DYNAMIC ADDRESS TRANSLATION WITH FORMAT CONTROL 有权
    动态地址翻译与格式控制

    公开(公告)号：US20090182964A1

    公开(公告)日：2009-07-16

    申请号：US11972706

    申请日：2008-01-11

    申请人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    发明人： DAN F. GREINER ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    IPC分类号： G06F12/10 ,  G06F12/14

    CPC分类号： G06F12/1009 ,  G06F2212/1044 ,  G06F2212/652

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If the format control field is enabled, a frame address of a large block of data in main storage is obtained from the translation table entry. The large block of data is a block of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a desired block of data within the large block of data in main storage. The desired large block of data addressed by the translated address is then accessed.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和翻译表的层次结构的转换表的初始起始地址。 虚拟地址的索引部分用于引用转换表中的条目。 如果启用格式控制字段，则从转换表条目获得主存储器中的大数据块的帧地址。 大块数据是至少1M字节的块。 然后将帧地址与虚拟地址的偏移部分组合，以在主存储器中的大量数据块内形成期望的数据块的转换地址。 然后访问由翻译的地址寻址的期望的大量数据。