公开(公告)号：US20050232044A1

公开(公告)日：2005-10-20

申请号：US11071351

申请日：2005-03-04

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L21/8242 ,  G11C7/02 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  H01L27/108

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： Due to the further scaling down, the offset of the sense amplifier is increased and the malfunction occurs in the read operation, and thus, the yield of the chip is degraded. For its prevention, a plurality of pull-down circuits and one pull-up circuit are used to constitute the sense amplifier circuit. Also, the transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of the transistor in the other pull-down circuit. Further, the pull-down circuit with a larger constant of the transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 由于进一步缩小，读取放大器的偏移增加，并且在读取操作中发生故障，因此芯片的产量降低。 为了防止，使用多个下拉电路和一个上拉电路来构成读出放大器电路。 此外，多个下拉电路之一中的晶体管具有诸如沟道长度或沟道宽度等于另一个下拉电路中的晶体管的沟道宽度的常数。 此外，首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US07995405B2

公开(公告)日：2011-08-09

申请号：US12967728

申请日：2010-12-14

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

公开(公告)号：US07973582B2

公开(公告)日：2011-07-05

申请号：US12205668

申请日：2008-09-05

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： H03H11/26

CPC分类号： H03K5/15033

摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

公开(公告)号：US07903492B2

公开(公告)日：2011-03-08

申请号：US12314860

申请日：2008-12-17

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

公开(公告)号：US07574648B2

公开(公告)日：2009-08-11

申请号：US11194486

申请日：2005-08-02

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C29/00

CPC分类号： G11C29/4401 ,  G11C11/401 ,  G11C29/42 ,  G11C29/44

摘要： When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention provides a DRAM that: has an error correcting code circuit for each sub-array; detects and corrects errors with said error correcting code circuit in both the reading and writing operations; and further has rescue circuits in addition to said error correcting code circuits and replaces a defective cell caused by hard error with a redundant bit.

摘要翻译： 当DRAM的小型化进展时，单元电容器的容量减小，数据线的电压降低，读取信号量显着降低，读出时产生误差，芯片的产量降低。 为了解决上述问题，本发明提供一种具有每个子阵列的纠错码电路的DRAM， 在读取和写入操作中检测和纠正所述纠错码电路的错误; 并且除了所述纠错码电路之外还具有救援电路，并用冗余位代替由硬错误引起的故障单元。

公开(公告)号：US07492655B2

公开(公告)日：2009-02-17

申请号：US11737693

申请日：2007-04-19

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20080181026A1

公开(公告)日：2008-07-31

申请号：US11963831

申请日：2007-12-22

申请人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

发明人： Hiroaki Nakaya ,  Riichiro Takemura ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Masayuki Nakamura ,  Shinichi Miyatake

IPC分类号： G11C7/08

CPC分类号： G11C11/4091 ,  G11C7/08 ,  G11C2207/005

摘要： In a semiconductor memory device, with respect to low voltage application, technique of controlling a gate voltage of a shared MOS transistor increasing sense speed and increasing data read speed by preventing data inversion caused by noise and reducing bit line capacitance during sensing is provided. By a shared MOS transistor gate voltage control circuit connecting a sense amplifier and a memory cell array, a shared MOS transistor gate voltage (SHR) is lowered in two stages and bit line capacitance to be amplified is reduced taking noise during the sensing into consideration so that the sense speed is increased. Therefore, a timing of activating a column selection signal can be hastened and as a result, data read time can be reduced.

摘要翻译： 在半导体存储器件中，关于低电压应用，提供了通过防止由噪声引起的数据反转和降低感测期间的位线电容来控制共享MOS晶体管的栅极电压提高感测速度并增加数据读取速度的技术。 通过连接读出放大器和存储单元阵列的共享MOS晶体管栅极电压控制电路，共享的MOS晶体管栅极电压（SHR）分为两级降低，并且在感测期间考虑到噪声，放大的位线电容降低 感觉速度增加。 因此，可以加快激活列选择信号的定时，结果可以减少数据读取时间。

公开(公告)号：US20070187736A1

公开(公告)日：2007-08-16

申请号：US11737693

申请日：2007-04-19

申请人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L29/94

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20110134678A1

公开(公告)日：2011-06-09

申请号：US12926693

申请日：2010-12-03

申请人： Takenori Sato ,  Kazuhiko Kajigaya ,  Yoshimitsu Yanagawa ,  Tomonori Sekiguchi ,  Akira Kotabe ,  Satoru Akiyama

发明人： Takenori Sato ,  Kazuhiko Kajigaya ,  Yoshimitsu Yanagawa ,  Tomonori Sekiguchi ,  Akira Kotabe ,  Satoru Akiyama

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/10876 ,  H01L27/10885

摘要： A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.

摘要翻译： 通过使用两个读出放大器进行时分执行相对于同时访问的两个存储单元的检测操作，然后同时执行恢复操作。 通过这种布置，不需要在全局位线的中间设置开关，并且在通过时分执行恢复操作时不会发生问题。 此外，由于第一读出放大器和第二读出放大器的寄生CR模型相互相同，因此可以保持高灵敏度。

公开(公告)号：US20060142988A1

公开(公告)日：2006-06-29

申请号：US11318431

申请日：2005-12-28

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Takayuki Kawahara ,  Kazuhiko Kajigaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10 ,  G06F2217/78

摘要： A manufacturing method for semiconductor memory and a semiconductor design device, which can facilitate design and reduce a period of time required for the design, are provided. For example, when a designed memory array is verified, a read-out signal of a memory cell formulated by functions of respective parameters having various distributions is used. A value of the read-out signal is calculated by using a value extracted randomly from the distribution for each kind of parameter. Quality of the memory cell is determined from a calculated result. Calculation of the value of the read-out signal and determination of the quality of the memory cell are carried out to a great number of memory cells the memory array has. The total number of failed bits and the like obtained from these is used as an evaluation criterion.

摘要翻译： 提供一种半导体存储器和半导体设计装置的制造方法，其可以促进设计并减少设计所需的时间。 例如，当设计的存储器阵列被验证时，使用由具有各种分布的各个参数的功能所制定的存储器单元的读出信号。 通过使用从各种参数的分布中随机提取的值来计算读出信号的值。 从计算结果确定存储单元的质量。 对存储器阵列具有的大量存储单元执行读出信号的值的计算和存储单元的质量的确定。 将从这些获得的故障比特等的总数用作评估标准。