公开(公告)号：US20090180343A1

公开(公告)日：2009-07-16

申请号：US12352347

申请日：2009-01-12

申请人： Satoru AKIYAMA ,  Riichiro TAKEMURA ,  Takayuki KAWAHARA ,  Tomonori SEKIGUCHI

发明人： Satoru AKIYAMA ,  Riichiro TAKEMURA ,  Takayuki KAWAHARA ,  Tomonori SEKIGUCHI

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20070187736A1

公开(公告)日：2007-08-16

申请号：US11737693

申请日：2007-04-19

申请人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru AKIYAMA ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L29/94

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20080055958A1

公开(公告)日：2008-03-06

申请号：US11976531

申请日：2007-10-25

申请人： Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Satoru HANZAWA ,  Tomonori SEKIGUCHI ,  Kazuhiko KAJIGAYA

发明人： Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Satoru HANZAWA ,  Tomonori SEKIGUCHI ,  Kazuhiko KAJIGAYA

IPC分类号： G11C5/06 ,  G11C11/24

CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873

摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

公开(公告)号：US20090066390A1

公开(公告)日：2009-03-12

申请号：US12205668

申请日：2008-09-05

申请人： Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

发明人： Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

IPC分类号： H03H11/26

CPC分类号： H03K5/15033

摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m.T1 + n。（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m.T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n的精细定时信号（T2 / L）。 m和n的值可以由寄存器设置。

公开(公告)号：US20080175084A1

公开(公告)日：2008-07-24

申请号：US11969223

申请日：2008-01-03

申请人： Satoru AKIYAMA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru AKIYAMA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

摘要翻译： 一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有 比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后 另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或 下拉电路失活。

公开(公告)号：US20080017904A1

公开(公告)日：2008-01-24

申请号：US11773990

申请日：2007-07-06

申请人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

发明人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.

摘要翻译： 提供了能够实现降低功耗，高速运行和高可靠性的DRAM。 构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。 为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。 多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。 因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

公开(公告)号：US20100109756A1

公开(公告)日：2010-05-06

申请号：US12686430

申请日：2010-01-13

申请人： Hiroaki NAKAYA ,  Satoru AKIYAMA ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA

发明人： Hiroaki NAKAYA ,  Satoru AKIYAMA ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA

IPC分类号： G05F1/10

CPC分类号： G11C5/146 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

摘要翻译： 一种防止工作速度降低的基板电压控制技术，并且相对于低电压使用而抑制由于阈值电压较低导致的漏电流。 由于通过多个复制MOS晶体管检测阈值电压的中心值，并且控制衬底电压以控制阈值电压的中心值，从而可以满足操作速度的下限和上限 整个芯片的漏电流。 另一方面，在芯片工作期间动态地控制衬底电压，从而可以在芯片工作时降低阈值电压的中心值以提高速度，并且增加阈值电压的中心值 芯片运行后降低整个芯片的漏电流。

公开(公告)号：US20120147244A1

公开(公告)日：2012-06-14

申请号：US13315393

申请日：2011-12-09

申请人： Satoru AKIYAMA

发明人： Satoru AKIYAMA

IPC分类号： H04N5/222

CPC分类号： H04N5/2259 ,  G03B17/18 ,  G03B2217/18 ,  H04N5/2252

摘要： An image pickup apparatus capable of giving a shooter the same rotary operation feeling regardless of the rotating direction, and displaying an erect image to a shooter at all times. A two-axis hinge is provided with a first bearing that supports a display unit rotatably in right and left directions and a second bearing that supports the display unit in rotated states rotatably so as to direct the screen to front and rear sides. A first axial rotation detector detects the rotation of the display unit by the first bearing. A second axial rotation detector detects the rotation of the display unit in the rotated states by the second bearing to direct the screen to the front and rear sides. A control unit switches display orientation of an image displayed on the display unit based on detection results from the first and second axial rotation detectors.

摘要翻译： 一种能够给予射手相同的旋转操作感觉而不管旋转方向如何的图像拾取装置，并且始终将直立图像显示给射手。 双轴铰链设置有第一轴承，该第一轴承可在左右方向上以可旋转的方式支撑显示单元;以及第二轴承，其可转动地支撑显示单元，以将屏幕导向前后侧。 第一轴向旋转检测器通过第一轴承检测显示单元的旋转。 第二轴向旋转检测器通过第二轴承检测显示单元在旋转状态下的旋转，以将屏幕引导到前侧和后侧。 控制单元基于来自第一和第二轴向旋转检测器的检测结果来切换显示在显示单元上的图像的显示方位。

公开(公告)号：US20110172883A1

公开(公告)日：2011-07-14

申请号：US13052503

申请日：2011-03-21

申请人： Koji MATSUNO ,  Satoru AKIYAMA ,  Shinji MATSUSHITA ,  Shiro EZOE ,  Masaru KOGURE ,  Hajime OYAMA

发明人： Koji MATSUNO ,  Satoru AKIYAMA ,  Shinji MATSUSHITA ,  Shiro EZOE ,  Masaru KOGURE ,  Hajime OYAMA

IPC分类号： B62D6/00

CPC分类号： B62D6/003 ,  B62D5/008

摘要： A steering control section has a first steering angle correction amount calculating section, a second steering angle correction amount calculating section, and a motor rotational angle calculating section. The first correction amount calculating section calculates a first correction amount based on a vehicle speed and an actual steering wheel angle. The second correction amount calculating section calculates a second correction amount through multiplying a control gain corresponding to the vehicle speed with a value calculated by low-pass filtering a differential value of steering wheel angle. The motor rotational angle calculating section calculates a motor rotational angle corresponding to the value adding the first and second steering angle correction amount, and outputs it to a motor driving section so as to drive an electric motor for correcting the steering angle. Thereby, an unstable vehicle behavior due to a resonance of a yaw motion caused in the steering operation can be suppressed.

摘要翻译： 转向控制部具有第一转向角修正量计算部，第二转向角修正量计算部和电动机转动角计算部。 第一校正量计算部基于车速和实际方向盘角度来计算第一校正量。 第二校正量计算部分通过将与车速相对应的控制增益乘以通过对方向盘角度的差分值进行低通滤波而计算的值来计算第二校正量。 马达旋转角度计算部分计算与增加第一和第二转向角校正量的值相对应的马达旋转角度，并将其输出到马达驱动部分，以驱动用于校正转向角的电动马达。 由此，可以抑制由于在转向操作中引起的偏航运动的共振引起的不稳定的车辆行为。