公开(公告)号：US10153287B1

公开(公告)日：2018-12-11

申请号：US15795247

申请日：2017-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ru Wang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chien-Hung Chen ,  Chun-Hsien Huang ,  Li-Ping Huang ,  Chun-Yen Tseng ,  Meng-Ping Chuang

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78 ,  H01L23/528 ,  H01L21/3213 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/092

Abstract: A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.

公开(公告)号：US20180182766A1

公开(公告)日：2018-06-28

申请号：US15422471

申请日：2017-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Ping Huang ,  Chun-Hsien Huang ,  Yu-Tse Kuo ,  Ching-Cheng Lung

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C7/02 ,  G11C7/14 ,  G11C7/22 ,  G11C11/4125 ,  H01L27/02 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1116

Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

公开(公告)号：US09947674B2

公开(公告)日：2018-04-17

申请号：US15686169

申请日：2017-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yu-Tse Kuo ,  Shu-Ru Wang

IPC: H01L27/11 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent pull-up FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

公开(公告)号：US09871048B1

公开(公告)日：2018-01-16

申请号：US15621754

申请日：2017-06-13

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.

公开(公告)号：US20170294429A1

公开(公告)日：2017-10-12

申请号：US15092630

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yung-Feng Cheng ,  Yu-Tse Kuo ,  Chia-Wei Huang ,  Li-Ping Huang ,  Shu-Ru Wang

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.

公开(公告)号：US09274416B2

公开(公告)日：2016-03-01

申请号：US14023476

申请日：2013-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Chia-Wei Huang ,  Hsin-Yu Chen ,  Kai-Lin Chuang

IPC: G03F1/72 ,  G03F1/00

CPC classification number: G03F1/72 ,  G03F1/144 ,  G03F1/36

Abstract: A method for forming a photo-mask is provided. A first photo-mask pattern relating to a first line, an original second photo-mask pattern relating to a first via plug, and a third photo-mask pattern relating to a second line are provided. A first optical proximity correction (OPC) process is performed. A second OPC process is performed, comprising enlarging a width of the second photo-mask pattern along the first direction to form a revised second photo-resist pattern. A contour simulation process is performed to make sure the revised second photo-mask pattern is larger or equal to the original second-mask pattern. The first photo-mask pattern, the revised second photo-mask pattern, and the third photo-mask pattern are output. The present invention further provides an OPC method.

Abstract translation: 提供一种形成光掩模的方法。 提供与第一行相关的第一照片掩模图案，与第一通孔插头相关的原始第二照片掩模图案和与第二行相关的第三照片掩模图案。 执行第一光学邻近校正（OPC）处理。 执行第二OPC处理，包括沿着第一方向放大第二光掩模图案的宽度以形成修改的第二光刻胶图案。 执行轮廓模拟处理以确保修改的第二光掩模图案大于或等于原始第二掩模图案。 输出第一光掩模图案，修改的第二光掩模图案和第三光掩模图案。 本发明还提供一种OPC方法。

公开(公告)号：US09268896B1

公开(公告)日：2016-02-23

申请号：US14576212

申请日：2014-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Hsien Tang ,  Shih-Hung Tsai ,  Chun-Hsien Huang ,  Yao-Jen Fan

IPC: G06F17/50

CPC classification number: G03F1/38 ,  G03F1/70 ,  G03F7/70425 ,  H01L21/823431

Abstract: A method of forming a photomask comprises providing a predetermined fin array having a plurality of fin patterns to a computer readable medium in a computer system. First of all, a plurality of width markers is defined by using the computer system, with each of the width marker parallel to each other and comprising two fin patterns, wherein each of the width markers is spaced from each other by a space. Then, a number of the width markers is checked to be an even. Following this, a plurality of pre-mandrel patterns is defined corresponding to odd numbered ones of the spaces. Then, a plurality of mandrel patterns is defined by sizing up the pre-mandrel patterns. Finally, the mandrel patterns are outputted to form a photomask.

Abstract translation: 形成光掩模的方法包括向计算机系统中的计算机可读介质提供具有多个鳍图案的预定鳍阵列。 首先，通过使用计算机系统来定义多个宽度标记，其中每个宽度标记彼此平行并且包括两个鳍图案，其中每个宽度标记彼此间隔一个空间。 然后，多个宽度标记被检查为均匀。 此后，对应于空格中的奇数编号的多个预心轴图案被定义。 然后，通过调整预心轴图案的尺寸来定义多个心轴图案。 最后，输出心轴图案以形成光掩模。