公开(公告)号：US20090040823A1

公开(公告)日：2009-02-12

申请号：US11946872

申请日：2007-11-29

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: G11C16/04

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: A flash memory is provided. A sawtooth gate conductor line, which interconnects the select gates of the select gate transistors arranged on the same column is provided. The sawtooth gate conductor line, which is disposed on both distal ends of a memory cell string, increases the integration of the flash memory. The sawtooth gate conductor line results in select gate transistors having different select gate lengths and produces at least one depletion-mode select transistor at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

Abstract translation: 提供闪存。 提供了将布置在同一列上的选择栅极晶体管的选通栅极互连的锯齿波导线。 设置在存储单元串的两个远端上的锯齿形栅极导线增加了闪速存储器的集成。 锯齿波导线导致选择栅极晶体管具有不同的选择栅极长度，并在存储单元串的一侧产生至少一个耗尽型选择晶体管。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US20090032860A1

公开(公告)日：2009-02-05

申请号：US11960720

申请日：2007-12-20

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang ,  Hsi-Hua Chang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang ,  Hsi-Hua Chang

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

Abstract: A programmable memory structure includes a substrate, an active area, a common-source and a common-drain respectively disposed on each side of the active area, a first and a second source contact electrically connected to the common-source, a first and a second drain contact electrically connected to the common-drain, and between the first and the second source contact and the first and the second drain contact a plurality of programmable memory cells including a first and a second dielectric layer respectively encapsulating a first and a second floating gate.

Abstract translation: 可编程存储器结构包括分别设置在有源区的每一侧上的衬底，有源区，公共源和公共漏极，电连接到共源的第一和第二源极触点，第一和 第二漏极接触电连接到共漏极，并且在第一和第二源极接触之间以及第一和第二漏极接触之间，多个可编程存储器单元包括分别封装第一和第二浮置的第一和第二介电层 门。

公开(公告)号：US07482227B1

公开(公告)日：2009-01-27

申请号：US11863282

申请日：2007-09-28

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/8247

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract translation: 一种用于制造闪速存储器的方法包括：提供具有牺牲氧化物层，牺牲多晶硅层，硬掩模层和暴露衬底部分的衬底并填充氧化物层的衬底，然后将氧化物层保形地 牺牲氧化物层和氧化物层，然后去除牺牲氧化物层上和氧化物层和牺牲氧化物层的顶部上的氧化物层，以形成作为STI氧化物间隔物的间隔物。

公开(公告)号：US20090011557A1

公开(公告)日：2009-01-08

申请号：US11863282

申请日：2007-09-28

Applicant: Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Mao-Quan Chen ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a flash memory includes providing a substrate with a sacrificial oxide layer, a sacrificial poly-Si layer, a hard mask layer and a trench exposing part of the substrate and filled with an oxide layer, later depositing a oxide layer conformally on the sacrificial oxide layer and the oxide layer, and afterwards removing the oxide layer on the sacrificial oxide layer and on the top of the oxide layer and the sacrificial oxide layer to form a spacer as a STI oxide spacer.

Abstract translation: 一种用于制造闪速存储器的方法包括：提供具有牺牲氧化物层，牺牲多晶硅层，硬掩模层和暴露衬底部分的衬底并填充氧化物层的衬底，然后将氧化物层保形地 牺牲氧化物层和氧化物层，然后去除牺牲氧化物层上和氧化物层和牺牲氧化物层的顶部上的氧化物层，以形成作为STI氧化物间隔物的间隔物。

公开(公告)号：US20130140620A1

公开(公告)日：2013-06-06

申请号：US13398853

申请日：2012-02-17

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L27/11524

Abstract: The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same.

Abstract translation: 本发明公开了一种闪速存储器。 闪速存储器包括依次设置在基板上的基板和存储器串，多个着陆焊盘，多个公共源极线，多个位线触点和至少一个位线。 该存储器串包括多个存储晶体管。 着陆焊盘设置在每个存储晶体管之间。 公共源线和位线接触件可替换地电连接到着陆焊盘。 公共线设置在公共线路触点上并与其电连接。 本发明还提供制造该方法的制造方法。

公开(公告)号：US08455363B2

公开(公告)日：2013-06-04

申请号：US13282593

申请日：2011-10-27

Applicant: Tzung-Han Lee ,  Chung-Lin Huang

Inventor： Tzung-Han Lee ,  Chung-Lin Huang

IPC: H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

Abstract: A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Abstract translation: 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US08298892B1

公开(公告)日：2012-10-30

申请号：US13241295

申请日：2011-09-23

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

IPC: H01L21/336

CPC classification number: H01L27/105 ,  H01L21/76224 ,  H01L29/4236

Abstract: A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.

Abstract translation: 一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。 制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。 第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。 第一个沟槽有第一个深度。 然后，去除第一掩埋结构的第一栅极。 之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。 最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

公开(公告)号：US08148766B2

公开(公告)日：2012-04-03

申请号：US12244295

申请日：2008-10-02

Applicant: Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/3185 ,  H01L29/42324 ,  H01L29/66825

Abstract: A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed.

Abstract translation: 提供非易失性存储单元。 提供半导体衬底。 导电层和间隔层顺序地设置在半导体衬底之上。 在导电层和间隔层中限定具有底部和多个侧表面的至少一个沟槽。 第一氧化物层形成在沟槽的底部。 在第一氧化物层，间隔层和沟槽的多个侧表面上形成介电层。 在沟槽中形成第一多晶硅层。 并且去除间隔层上的电介质层的第一部分，从而形成用于非易失性存储单元的基本结构。

公开(公告)号：US20120012907A1

公开(公告)日：2012-01-19

申请号：US12874232

申请日：2010-09-02

Applicant: Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

Inventor： Tzung-Han Lee ,  Chung-Lin Huang ,  Hsien-Wen Liu

IPC: H01L27/108

CPC classification number: H01L29/4983 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10882 ,  H01L29/4236

Abstract: A memory layout structure is disclosed, in which, a lengthwise direction of each active area and each row of active areas form an included angle not equal to zero and not equal to 90 degrees, bit lines and word lines cross over each other above the active areas, the bit lines are each disposed above a row of active areas, bit line contact plugs or node contact plugs may be each disposed entirely on an source/drain region, or partially on the source/drain region and partially extend downward along a sidewall (edge wall) of the substrate of the active area to carry out a sidewall contact. Self-aligned node contact plugs are each disposed between two adjacent bit lines and between two adjacent word lines.

Abstract translation: 公开了一种存储器布局结构，其中每个有效区域和每行有效区域的长度方向形成不等于零且不等于90度的夹角，位线和字线在有效区域之上彼此交叉 位线各自设置在有效区域的一行之上，位线接触插塞或节点接触插塞可以各自完全设置在源极/漏极区域上，或者部分地设置在源极/漏极区域上，并且部分地沿着侧壁向下延伸 （边缘壁），以执行侧壁接触。 自对准节点接触插头各自设置在两个相邻位线之间和两个相邻字线之间。

公开(公告)号：US07972924B2

公开(公告)日：2011-07-05

申请号：US12839387

申请日：2010-07-19

Applicant: Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

Inventor： Hung-Mine Tsai ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC: H01L21/336

CPC classification number: H01L27/11521

Abstract: A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer.

Abstract translation: 一种用于制造存储器的方法，包括首先提供具有水平相邻的控制栅极区域和浮置栅极区域的衬底，该栅极区域包括牺牲层和牺牲侧壁，去除牺牲层和牺牲侧壁以露出衬底，形成邻近控制的电介质侧壁 栅极区域，在暴露的衬底上形成浮栅电介质层，并形成与电介质侧壁相邻的浮栅极和浮置栅极电介质层。