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    Flash Memory and Manufacturing Method Thereof
    3.
    发明申请
    Flash Memory and Manufacturing Method Thereof 审中-公开
    闪存及其制造方法

    公开(公告)号：US20130140620A1

    公开(公告)日：2013-06-06

    申请号：US13398853

    申请日：2012-02-17

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L27/11524

    摘要： The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same.

    摘要翻译： 本发明公开了一种闪速存储器。 闪速存储器包括依次设置在基板上的基板和存储器串，多个着陆焊盘，多个公共源极线，多个位线触点和至少一个位线。 该存储器串包括多个存储晶体管。 着陆焊盘设置在每个存储晶体管之间。 公共源线和位线接触件可替换地电连接到着陆焊盘。 公共线设置在公共线路触点上并与其电连接。 本发明还提供制造该方法的制造方法。

    FLASH MEMORY STRUCTURE
    4.
    发明申请
    FLASH MEMORY STRUCTURE 审中-公开
    闪存存储器结构

    公开(公告)号：US20130062676A1

    公开(公告)日：2013-03-14

    申请号：US13239364

    申请日：2011-09-21

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu ,  Dah-Wei Liu

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L29/40114

    摘要： A flash memory structure includes a semiconductor substrate, a gate dielectric layer on the semiconductor substrate, a floating gate on the gate dielectric layer, a capacitor dielectric layer conformally covering the floating gate, wherein the capacitor dielectric layer forms a top surface and four sidewall surfaces; and an isolated conductive cap layer covering the top surface and the four sidewall surfaces.

    摘要翻译： 闪速存储器结构包括半导体衬底，半导体衬底上的栅极电介质层，栅极介电层上的浮置栅极，保形地覆盖浮置栅极的电容器电介质层，其中电容器介电层形成顶表面和四个侧壁表面 ; 以及覆盖顶表面和四个侧壁表面的隔离的导电盖层。

    Method Of Memory Array And Structure Form
    5.
    发明申请
    Method Of Memory Array And Structure Form 审中-公开
    存储器阵列和结构形式的方法

    公开(公告)号：US20130146954A1

    公开(公告)日：2013-06-13

    申请号：US13429448

    申请日：2012-03-26

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/10876 ,  H01L27/10885

    摘要： The present invention provides a memory array including a substrate, an isolation region, a plurality of active regions, a plurality of buried bit lines, a plurality of word lines, a plurality of drain regions and a plurality of capacitors. The isolation region and the active regions are disposed in the substrate and the active regions are encompassed and isolated by the isolation region. The buried bit lines are disposed in the substrate and extend in the second direction. The word lines are disposed in the substrate extend in the first direction. The drain regions are disposed in the active region not covered by the word lines. The capacitors are disposed on the substrate and electrically connected to the drain regions.

    摘要翻译： 本发明提供了一种存储器阵列，其包括衬底，隔离区，多个有源区，多个掩埋位线，多个字线，多个漏极区和多个电容。 隔离区域和有源区域设置在衬底中，并且有源区域被隔离区域包围和隔离。 掩埋位线设置在基板中并沿第二方向延伸。 字线设置在基板中沿第一方向延伸。 漏极区域设置在未被字线覆盖的有源区域中。 电容器设置在基板上并电连接到漏极区域。

    Fabricating method of insulator
    6.
    发明授权
    Fabricating method of insulator 有权
    绝缘子的制造方法

    公开(公告)号：US08298892B1

    公开(公告)日：2012-10-30

    申请号：US13241295

    申请日：2011-09-23

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L29/4236

    摘要： A fabricating method of an insulator for replacing a gate structure in a substrate by the insulator. The fabricating method includes the step of providing a substrate including a first buried gate structure. The first buried structure includes a first trench embedded in the substrate and a first gate filling in the first trench. The first trench has a first depth. Then, the first gate of the first buried structure is removed. Later, the substrate under the first trench is etched to elongate the depth of the first trench from the first depth to a third depth. Finally, an insulating material fills in the first trench with the third depth to form an insulator of the present invention.

    摘要翻译： 一种绝缘体的制造方法，用于通过绝缘体代替衬底中的栅极结构。 制造方法包括提供包括第一掩埋栅极结构的衬底的步骤。 第一掩埋结构包括嵌入衬底中的第一沟槽和填充在第一沟槽中的第一栅极。 第一个沟槽有第一个深度。 然后，去除第一掩埋结构的第一栅极。 之后，蚀刻第一沟槽下面的衬底，以将第一沟槽的深度从第一深度延伸到第三深度。 最后，绝缘材料填充具有第三深度的第一沟槽以形成本发明的绝缘体。

    High-k metal gate random access memory
    7.
    发明授权
    High-k metal gate random access memory 有权
    高k金属门随机存取存储器

    公开(公告)号：US08779494B2

    公开(公告)日：2014-07-15

    申请号：US13426825

    申请日：2012-03-22

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

    摘要： The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions. The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.

    摘要翻译： 本公开涉及高k金属栅极随机存取存储器。 存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。 衬底具有多个沟槽，并且位线单元布置在衬底上。 源极区域设置在位线单元上，栅极结构设置在源极区域上。 每个栅极结构具有形成在其中的金属栅极和沟道区域。 栅极结构顶部带有漏极区域。 字线单元布置在源区和漏区之间。 电容单元设置在漏极区域上。 还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

    Manufacturing method of random access memory
    8.
    发明授权
    Manufacturing method of random access memory 有权
    随机存取存储器的制造方法

    公开(公告)号：US08703562B2

    公开(公告)日：2014-04-22

    申请号：US13426832

    申请日：2012-03-22

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron-Fu Chu

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.

    摘要翻译： 随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。

    MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE
    9.
    发明申请
    MEMORY LAYOUT STRUCTURE AND MEMORY STRUCTURE 有权
    存储器布局结构和存储器结构

    公开(公告)号：US20130119448A1

    公开(公告)日：2013-05-16

    申请号：US13343668

    申请日：2012-01-04

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10891 ,  H01L28/90

    摘要： A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.

    摘要翻译： 存储器阵列布局包括具有多个有源区域的有源区域阵列，其中有源区域沿着第二方向交替布置，并且相邻有源区域的一部分侧沿第二方向重叠; 多个第一掺杂区域，其中每个第一掺杂区域设置在中间区域中; 多个第二掺杂区域，其中每个第二掺杂区域分别设置在远端区域中; 多个凹入栅结构; 分别电连接到每个凹入栅结构的多个字线; 分别电连接到第一掺杂区的多个数字线; 以及分别与每个第二掺杂区域电连接的多个电容器。

    FABRICATING METHOD OF DRAM STRUCTURE
    10.
    发明申请
    FABRICATING METHOD OF DRAM STRUCTURE 有权
    DRAM结构的制作方法

    公开(公告)号：US20130052786A1

    公开(公告)日：2013-02-28

    申请号：US13297276

    申请日：2011-11-16

    申请人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    发明人： Tzung-Han Lee ,  Chung-Lin Huang ,  Ron Fu Chu

    IPC分类号： H01L21/02

    CPC分类号： H01L27/10894 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/66545

    摘要： A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.

    摘要翻译： DRAM结构的制造方法包括提供包括存储器阵列区域和外围区域的衬底。 掩埋栅极晶体管设置在存储器阵列区域内，并且平面栅极晶体管设置在周边区域内。 此外，层间电介质层覆盖存储器阵列区域，掩埋栅极晶体管和平面栅极晶体管。 然后，同时去除平面栅晶体管的覆盖层和层间电介质层的一部分，使得在层间电介质层中形成第一接触孔，第二接触孔和第三接触孔。 埋入栅极晶体管的漏极掺杂区域通过第一接触孔露出，平面栅极晶体管的掺杂区域通过第二接触孔露出，平面栅极晶体管的栅电极通过第三接触孔露出。