公开(公告)号：US07805258B2

公开(公告)日：2010-09-28

申请号：US11707662

申请日：2007-02-16

申请人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

发明人： Hsueh-Hung Fu ,  Chih-Wei Chang ,  Shih-Chang Chen ,  Chin-Piao Chang ,  Shing-Chyang Pan ,  Wei-Jung Lin ,  Tsung-Hsun Huang

IPC分类号： G06F19/00 ,  G06F17/40

CPC分类号： G01R31/2831 ,  H01L22/12

摘要： A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer.

摘要翻译： 在晶片上形成当前顶层之后测试晶片的方法。 在形成当前顶层之后，为晶片收集应力数据。 应力数据来源于晶片曲率的变化。 应力数据包括：在x方向上的应力x x和在晶片上的一组有限区域的每个区域的ay方向上的应力yy，应力xx和应力yy都源自晶片曲率变化 - x x在x方向上对于有限区域集合中的每个区域以及从y方向的晶片曲率变化yy到该有限区域集合中的每个区域; 并且应力xy从晶片曲率变化xy得到，其中晶片曲率变化xy是在该有限区域的每个区域的x-y平面中的晶片扭转的变化。 应力梯度矢量（和/或其范数）被计算并用于评估调查单个或多个累积层。

公开(公告)号：US20100015814A1

公开(公告)日：2010-01-21

申请号：US12176655

申请日：2008-07-21

申请人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/45 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

摘要翻译： 提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。 对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。 应力诱导层可以是凹陷区域或非凹陷区域。 第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。 在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。 另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

公开(公告)号：US20090137119A1

公开(公告)日：2009-05-28

申请号：US11946489

申请日：2007-11-28

申请人： Hsin-Lun Liu ,  Huan-Just Lin ,  Shih-Chang Chen

发明人： Hsin-Lun Liu ,  Huan-Just Lin ,  Shih-Chang Chen

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76831

摘要： A method is disclosed for etching a contact hole in a stack of dielectric layers. The method minimizes bridging defects between the contact hole and adjacent conductive structures. A substrate has a conductive material layer and an active device disposed thereon. An etch stop layer covers the device and the conductive material, A layer of interlevel dielectric and antireflective coating layers are then provided. A hole is etched through the stack using patterned photoresist. Ashing is used to remove all but the etch stop layer and the interlevel dielectric layer. An isolation liner is deposited over the interlevel dielectric layer, the sidewall surfaces of the hole and the exposed upper surface of the etch stop layer. Another etch removes the isolation liner disposed over the exposed upper surface of the etch stop layer, and removes the underlying etch stop layer to expose an upper surface of the conductive material layer.

摘要翻译： 公开了一种用于蚀刻电介质层叠层中的接触孔的方法。 该方法使接触孔和相邻导电结构之间的桥接缺陷最小化。 衬底具有导电材料层和设置在其上的有源器件。 蚀刻停止层覆盖器件和导电材料，然后提供层间介电层和抗反射涂层层。 使用图案化的光致抗蚀剂，通过堆叠蚀刻孔。 灰化用于除去蚀刻停止层和层间电介质层以外的全部。 隔离衬垫沉积在层间介电层上，孔的侧壁表面和蚀刻停止层的暴露的上表面。 另外的蚀刻去除了设置在蚀刻停止层的暴露的上表面上方的隔离衬垫，并去除下面的蚀刻停止层以暴露导电材料层的上表面。

公开(公告)号：US07528028B2

公开(公告)日：2009-05-05

申请号：US11199011

申请日：2005-08-08

申请人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Mong Song Liang ,  Chien-Hao Chen ,  Chun-Feng Nieh ,  Pang-Yen Tsai ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/7624 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

摘要翻译： 一种用于形成半导体结构的方法包括：提供衬底，在衬底上形成第一器件区域，形成覆盖第一器件区域的应力层，以及对第一器件区域中的应力层进行超退火，优选通过将衬底暴露于 高能量辐射源，使得应力层在超短时间内进行超退火。 优选地，该方法还包括在第一器件区域被超退火时掩蔽衬底上的第二器件区域。 或者，在第一区域中的应力层退火之后，第二器件区域中的应力层被超退火。 使用该方法形成的半导体结构在第一和第二器件区域中具有不同的应变。

公开(公告)号：US20080124861A1

公开(公告)日：2008-05-29

申请号：US11593293

申请日：2006-11-06

申请人： Wenli Lin ,  Da-Yuan Lee ,  Chi-Chun Chen ,  Shih-Chang Chen

发明人： Wenli Lin ,  Da-Yuan Lee ,  Chi-Chun Chen ,  Shih-Chang Chen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/6656

摘要： A semiconductor structure includes a PMOS device and an NMOS device. The PMOS device includes a first gate dielectric on a semiconductor substrate, a first gate electrode on the first gate dielectric, and a first gate spacer along sidewalls of the first gate electrode and the first gate dielectric. The NMOS device includes a second gate dielectric on the semiconductor substrate, a second gate electrode on the second gate dielectric, a nitrided polysilicon re-oxidation layer having a vertical portion and a horizontal portion wherein the vertical portion is on sidewalls of the second gate electrode and the second gate dielectric and wherein the horizontal portion is on the semiconductor substrate, and a second gate spacer on sidewalls of the second gate electrode and the second gate dielectric, wherein the second gate spacer is on the horizontal portion of the nitrided polysilicon re-oxidation layer.

摘要翻译： 半导体结构包括PMOS器件和NMOS器件。 PMOS器件包括半导体衬底上的第一栅极电介质，第一栅极电介质上的第一栅极电极和沿着第一栅极电极和第一栅极电介质的侧壁的第一栅极间隔物。 所述NMOS器件包括在所述半导体衬底上的第二栅极电介质，所述第二栅极电介质上的第二栅极电极，具有垂直部分和水平部分的氮化多晶硅再氧化层，其中所述垂直部分位于所述第二栅电极的侧壁上 和所述第二栅极电介质，并且其中所述水平部分在所述半导体衬底上，以及在所述第二栅极电极和所述第二栅极电介质的侧壁上的第二栅极间隔物，其中所述第二栅极间隔物位于所述氮化多晶硅的水平部分上， 氧化层。

公开(公告)号：US07335544B2

公开(公告)日：2008-02-26

申请号：US11012413

申请日：2004-12-15

申请人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

发明人： Chien-Hao Chen ,  Donald Y. Chao ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC分类号： H01L29/739

CPC分类号： H01L29/7833 ,  H01L29/6659 ,  H01L29/7843

摘要： A metal-oxide-semiconductor field-effect transistors (MOSFET) having localized stressors is provided. In accordance with embodiments of the present invention, a transistor comprises a high-stress film over the source/drain regions, but not over the gate electrode. The high-stress film may be a tensile-stress film for use with n-channel devices or a compressive-stress film for use with p-channel devices. A method of fabricating a MOSFET with localized stressors over the source/drain regions comprises forming a transistor having a gate electrode and source/drain regions, forming a high-stress film over the gate electrode and the source/drain regions, and thereafter removing the high-stress film located over the gate electrode, thereby leaving the high-stress film located over the source/drain regions. A contact-etch stop layer may be formed over the transistor.

摘要翻译： 提供了具有局部应力源的金属氧化物半导体场效应晶体管（MOSFET）。 根据本发明的实施例，晶体管包括源/漏区上的高应力膜，但不在栅电极上。 高应力膜可以是用于n沟道器件的拉伸应力膜或用于p沟道器件的压应力膜。 在源极/漏极区域上制造具有局部应力源的MOSFET的方法包括形成具有栅电极和源极/漏极区的晶体管，在栅电极和源极/漏极区上形成高应力膜，然后除去 高应力膜位于栅电极之上，从而使高应力膜位于源极/漏极区之上。 接触蚀刻停止层可以形成在晶体管上。

公开(公告)号：US20070166904A1

公开(公告)日：2007-07-19

申请号：US11333399

申请日：2006-01-17

申请人： Jocelyn Teo ,  Chi-Chun Chen ,  Shih-Chang Chen

发明人： Jocelyn Teo ,  Chi-Chun Chen ,  Shih-Chang Chen

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L21/823857

摘要： The preferred embodiment of the present invention provides a novel method of forming MOS devices using hydrogen annealing. The method includes providing a semiconductor substrate including a first region and a second region, forming at least a portion of a first MOS device covering at least a portion of the first active region, performing a hydrogen annealing in an ambient containing substantially pure hydrogen on the semiconductor substrate. The hydrogen annealing is performed after the step of the at least a portion of the first MOS device is formed, and preferably after a pre-oxidation cleaning. The method further includes forming a second MOS device in the second active region after hydrogen annealing. The hydrogen annealing causes the surface of the second active region to be substantially rounded, while the surface of the first active region is substantially flat.

摘要翻译： 本发明的优选实施方案提供了使用氢退火形成MOS器件的新方法。 该方法包括提供包括第一区域和第二区域的半导体衬底，形成覆盖第一有源区域的至少一部分的第一MOS器件的至少一部分，在包含基本上纯氢的环境中进行氢退火 半导体衬底。 氢退火在形成第一MOS器件的至少一部分的步骤之后，优选在预氧化清洗之后进行。 该方法还包括在氢退火之后在第二有源区中形成第二MOS器件。 氢退火使得第二有源区的表面基本上是圆形的，而第一有源区的表面基本上是平的。

公开(公告)号：US07229919B2

公开(公告)日：2007-06-12

申请号：US10870878

申请日：2004-06-17

申请人： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/44

CPC分类号： H01L21/28044 ,  C23C16/24 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28052 ,  H01L29/4925

摘要： A semiconductor device having a random grained polysilicon layer and a method for its manufacture are provided. In one example, the device includes a semiconductor substrate and an insulator layer on the substrate. A first polysilicon layer having a random grained structure is positioned above the insulator layer, a semiconductor alloy layer is positioned above the first polysilicon layer, and a second polysilicon layer is positioned above the semiconductor alloy layer.

摘要翻译： 提供了具有随机晶粒多晶硅层的半导体器件及其制造方法。 在一个示例中，该器件在衬底上包括半导体衬底和绝缘体层。 具有随机晶粒结构的第一多晶硅层位于绝缘体层的上方，半导体合金层位于第一多晶硅层的上方，第二多晶硅层位于半导体合金层的上方。

公开(公告)号：US20070063282A1

公开(公告)日：2007-03-22

申请号：US11599931

申请日：2006-11-15

申请人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

发明人： Ji-Yi Yang ,  Chien-Hao Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Huan-Just Lin

IPC分类号： H01L27/12 ,  H01L29/00

CPC分类号： H01L21/3247 ,  H01L21/76232 ,  H01L21/76283 ,  H01L27/1203

摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

摘要翻译： 通过退火将体硅转变成SOI样结构。 沟槽形成在大量衬底中以限定器件位置。 沟槽的下部在氢气气氛中在低压下退火。 这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。 相邻的空洞每个居住在中间位置的一半左右。 消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

公开(公告)号：US07166525B2

公开(公告)日：2007-01-23

申请号：US10758317

申请日：2004-01-15

申请人： Vincent S. Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

发明人： Vincent S. Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

IPC分类号： H01L21/4763 ,  H01L21/3205

CPC分类号： H01L29/518 ,  H01L21/28123 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/32137 ,  H01L29/6659

摘要： A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

摘要翻译： 已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。 在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。 高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。 当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。 因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。