公开(公告)号：US20060149861A1

公开(公告)日：2006-07-06

申请号：US11029891

申请日：2005-01-05

申请人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Kahle ,  Charles Johns ,  Michael Day ,  Peichun Liu

发明人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Kahle ,  Charles Johns ,  Michael Day ,  Peichun Liu

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

摘要翻译： 方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作 与共享存储器和DMAC的通信可操作地耦合到本地存储器。

公开(公告)号：US07032923B2

公开(公告)日：2006-04-25

申请号：US10419136

申请日：2003-04-21

申请人： Norihiro Kurata ,  Takeshi Yamazaki ,  Takeshi Kuroe

发明人： Norihiro Kurata ,  Takeshi Yamazaki ,  Takeshi Kuroe

IPC分类号： B60R21/16

CPC分类号： B60R21/2338 ,  B60R21/20 ,  B60R21/2171 ,  B60R2021/0088 ,  B60R2021/23107 ,  B60R2021/23386 ,  B62J27/00

摘要： To provide an air bag apparatus for a small size vehicle, wherein a seat for a driver is provided at a rear portion of a vehicle body and an instrument panel, which a driver on the seat can visually observe is provided at a front portion of the vehicle body. The air bag apparatus assures a wide range of inflation and expansion of an air bag and can be applied to a conventional small size vehicle without a significant design change. A plurality of air bags which can constrain a driver on a seat from a forward direction are connected to each other by a connection mechanism and are accommodated in a folded state in an instrument panel.

摘要翻译： 为了提供一种用于小型车辆的气囊装置，其中在车身的后部设置有用于驾驶员的座椅和仪表板，座椅上的驾驶员可以在视觉上观察到座椅，该前部部分 车身。 气囊装置确保了气囊的宽范围膨胀和膨胀，并且可以应用于传统的小型车辆而没有显着的设计变化。 可以通过连接机构将能够将驾驶员从前方向限制在座椅上的多个气囊，并且以折叠状态容纳在仪表板中。

公开(公告)号：US20050251649A1

公开(公告)日：2005-11-10

申请号：US11110492

申请日：2005-04-20

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F9/38 ,  G06F12/06 ,  G06F15/00 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F12/0607

摘要： Methods and systems are disclosed for staggered address mapping of memory regions in shared memory for use in multi-threaded processing of single instruction multiple data (SIMD) threads and multi-scalar threads without inter-thread memory region conflicts and permitting transition from SIMD mode to multi-scalar mode without the need for rearrangement of data stored in the memory regions.

摘要翻译： 公开了用于共享存储器中的存储器区域的交错地址映射的方法和系统，用于单线程多数据（SIMD）线程和多标量线程的多线程处理，而不需要线程间存储器区域冲突，并允许从SIMD模式转换到 多标量模式，而不需要重新排列存储在存储器区域中的数据。

公开(公告)号：US20050251648A1

公开(公告)日：2005-11-10

申请号：US11108959

申请日：2005-04-19

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F9/38 ,  G06F9/318 ,  G06F15/00 ,  G06F17/50

CPC分类号： G06F9/3885 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/3822 ,  G06F9/3851 ,  G06F17/5045

摘要： A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. Each such issue logic unit is operable to control execution of the instruction by one or more functional units according to a common instruction set. When the processor includes a plurality of functional units, the at least one issue logic unit is operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit is further operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units, wherein each subset is operated according to a respective one of the multiple instructions.

摘要翻译： 提供一种具有模块化组织的处理器，该模块化组织包括至少一个可操作以存储用于执行的数据和指令的本地存储器，至少一个功能单元，可操作以执行从本地存储器提供的数据上的指令，以及至少一个发行逻辑单元， 将从本地商店提供的指令转换为用于执行指令的功能单元的操作。 每个这样的发行逻辑单元可操作以根据公共指令集来控制由一个或多个功能单元执行指令。 当处理器包括多个功能单元时，至少一个发行逻辑单元可操作以解码从本地存储器提供的统一指令，以根据单一指令同时操作所有功能单元。 每个问题逻辑单元进一步可操作以解码多个指令以单独操作多个功能单元的第一和第二子集，其中每个子集根据多个指令中的相应一个来操作。

公开(公告)号：US20050125581A1

公开(公告)日：2005-06-09

申请号：US10730952

申请日：2003-12-09

申请人： Jeffrey Brown ,  Scott Clark ,  Charles Johns ,  Takeshi Yamazaki

发明人： Jeffrey Brown ,  Scott Clark ,  Charles Johns ,  Takeshi Yamazaki

IPC分类号： G06F13/14 ,  G06F13/362

CPC分类号： G06F13/3625

摘要： An improved method and apparatus for resource arbitration. Four priority classes, managed high (MH), managed low (ML), opportunistic high (OH) and opportunistic low (OL), are defined. A priority class is assigned to each resource access request. An access request concentrator (ARC) is created for each resource, through which the resource is accessed. An access request is chosen at each ARC using the priority order MH, ML, OH, and OL, in decreasing order of priority. If OH priority class resource access requests are locked out, the priority order is temporarily changed to OH, OL, MH, and ML, in decreasing order of priority. If OL priority class resource access requests are locked out, the priority order is temporarily changed to MH, OL, OH, and ML, in decreasing order of priority.

摘要翻译： 一种改进的资源仲裁方法和装置。 定义了四个优先级，管理高（MH），管理低（ML），机会高（OH）和机会主义低（OL）。 优先级分配给每个资源访问请求。 为每个资源创建访问请求集中器（ARC），通过该资源访问资源。 在优先级顺序为MH，ML，OH和OL的每个ARC中选择访问请求。 如果OH优先级资源访问请求被锁定，优先级顺序将按照优先级的降序暂时更改为OH，OL，MH和ML。 如果OL优先级资源访问请求被锁定，优先级顺序将按照优先级的降序临时更改为MH，OL，OH和ML。

公开(公告)号：US20050120254A1

公开(公告)日：2005-06-02

申请号：US10959700

申请日：2004-10-05

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F1/26 ,  G06F12/00

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/3243 ,  G06F9/30145 ,  G06F9/30167 ,  Y02D10/152 ,  Y02D10/16

摘要： A processing element (PE) includes a processing unit (PU) and a number of attached processing units (APUs). The instruction set of each APU is divided a priori into a number of types, each type associated with a different amount of heat generation. Each APU keeps track of the amount of each type of instruction executed over a time period,—the power information,—and provides this power information to the PU. The PU then performs power management as a function of the provided power information from each APU,—such as directing a particular APU to enter an idle state to reduce power consumption.

摘要翻译： 处理单元（PE）包括处理单元（PU）和多个附加处理单元（APU）。 每个APU的指令集被预先划分成多种类型，每种类型与不同的发热量相关联。 每个APU跟踪在一段时间内执行的每种类型的指令的数量 - 功率信息，并将该功率信息提供给PU。 然后，PU根据来自每个APU的所提供的功率信息执行功率管理，例如指示特定APU进入空闲状态以降低功耗。

公开(公告)号：US20050081209A1

公开(公告)日：2005-04-14

申请号：US10967433

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06 ,  G06F9/46

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。

公开(公告)号：US06549676B1

公开(公告)日：2003-04-15

申请号：US09412432

申请日：1999-10-05

申请人： Tadayoshi Nakayama ,  Hiroshi Kajiwara ,  Takeshi Yamazaki

发明人： Tadayoshi Nakayama ,  Hiroshi Kajiwara ,  Takeshi Yamazaki

IPC分类号： G06K936

CPC分类号： G06T9/004

摘要： The objective of the present invention is to perform fast variable-length coding that is applied for lossless compression and encoding. To achieve this objective, an encoding device comprises a unit for determining, from a plurality of states, states of peripheral pixels of an object pixel to be encoded, a unit for producing a predicted value of the object pixel based on the peripheral pixels, a memory used for storing a k parameter (k≦0) for each of the plurality of states, a unit for encoding a prediction difference between the value of the object pixel and a predicted value to variable-length code having a code length that is obtained by using the prediction difference and the k parameter that is stored in the memory and corresponds to the state determined by the state determination unit and a unit for, after variable-length encoding is performed for the object pixel, updating in advance the k parameter in order to perform variable-length encoding for another pixel that has the same state as the state determined by the state determination unit, and for writing the k parameter to the memory.

摘要翻译： 本发明的目的是执行用于无损压缩和编码的快速可变长度编码。 为了实现该目的，编码装置包括用于从多个状态确定要编码的对象像素的周边像素的状态的单元，用于基于周边像素产生对象像素的预测值的单元， 用于存储多个状态中的每一个的ak参数（k <= 0）的存储器，用于将对象像素的值与预测值之间的预测差编码为具有获得的代码长度的可变长度代码的单元 通过使用存储在存储器中的预测差和k参数，并且对应于由状态确定单元确定的状态，并且在针对对象像素执行可变长度编码之后的单元，预先更新k参数 为与由状态判定单元确定的状态具有相同状态的另一像素执行可变长度编码，并将k参数写入存储器。

公开(公告)号：US06546129B1

公开(公告)日：2003-04-08

申请号：US08963984

申请日：1997-11-04

申请人： Takatoshi Ohta ,  Ryuichi Arai ,  Munehiko Ohta ,  Hiroaki Sugiura ,  Toshihiro Nakazawa ,  Takeshi Yamazaki

发明人： Takatoshi Ohta ,  Ryuichi Arai ,  Munehiko Ohta ,  Hiroaki Sugiura ,  Toshihiro Nakazawa ,  Takeshi Yamazaki

IPC分类号： G06K900

CPC分类号： H04N1/00867 ,  G07D7/12 ,  G07D7/20 ,  H04N1/0087 ,  H04N2201/3205 ,  H04N2201/327

摘要： In case of managing image data among plural image processing apparatuses, an object of the present invention is to suppress or restrain, as much as possible, that the image data is illegally or unfairly used. In order to achieve the object, e.g., it is provided an image processing apparatus which is connected to an external apparatus being an output destination of the image data, the image processing apparatus comprises an input means for inputting the image data representing an image, an addition means for adding additional information capable of specifying the external apparatus to the image data inputted by the input means, in a state that the additional information is difficult to be perceived by human eyes, and an output means for outputting the image data to which the additional information was added by the addition means, to the external apparatus.

摘要翻译： 在多个图像处理装置中管理图像数据的情况下，本发明的目的是尽可能地抑制或限制图像数据被非法或不公平地使用。 为了实现该目的，例如，提供了连接到作为图像数据的输出目的地的外部设备的图像处理装置，图像处理装置包括用于输入表示图像的图像数据的输入装置， 附加装置，用于在附加信息难以被人眼察觉的状态下，将能够指定外部装置的附加信息添加到由输入装置输入的图像数据;以及输出装置，用于输出图像数据， 通过添加装置将附加信息添加到外部设备。

公开(公告)号：US6054793A

公开(公告)日：2000-04-25

申请号：US159713

申请日：1998-09-24

申请人： Yutaka Kawai ,  Takeshi Yamazaki

发明人： Yutaka Kawai ,  Takeshi Yamazaki

IPC分类号： H01L41/08 ,  H01L41/083 ,  H03H20060101 ,  H03H3/04 ,  H03H9/00 ,  H03H9/02 ,  H03H9/10 ,  H03H9/15 ,  H03H9/17 ,  H03H9/205 ,  H03H9/58 ,  H04B1/26

CPC分类号： H03H9/178 ,  H03H3/04 ,  H03H9/1014

摘要： A base member of a piezoelectric resonator includes a laminated body having a plurality of piezoelectric layers which are alternately polarized in opposite directions along the longitudinal direction of the base member and inner electrodes provided between the piezoelectric layers. On a first side surface of the base member, each of two external electrodes is arranged so as to be connected to one of two groups of alternate inner electrodes. Cut portions for adjusting a frequency of the piezoelectric resonator to a higher frequency are respectively formed at edge portions of the base member at opposite ends in the longitudinal direction of a second side surface opposite from the first side surface of the base member.

摘要翻译： 压电谐振器的基座部件包括具有多个压电层的叠层体，所述多个压电层沿着基底部件的长度方向相反的方向交替极化，而内部电极设置在压电层之间。 在基体的第一侧表面上，两个外部电极中的每一个被布置成连接到两组交替的内部电极中的一组。 用于将压电谐振器的频率调节到较高频率的切割部分分别形成在与基底构件的第一侧表面相对的第二侧表面的纵向方向上的相对端处的基底构件的边缘部分处。