公开(公告)号：US20090147587A1

公开(公告)日：2009-06-11

申请号：US11951262

申请日：2007-12-05

申请人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

发明人： Tien-Chun Yang ,  Yonggang Wu ,  Nian Yang

IPC分类号： G11C16/00

CPC分类号： G11C16/30 ,  G11C7/12 ,  G11C16/24

摘要： Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.

摘要翻译： 通常，存储线的读取时间由于电压过冲和/或电压下冲而变慢。 为了消除这些问题，控制部件可以管理电压，同时泄漏部件管理电压的时序。 这允许产生增加读取时间的线路预充电。 控制组件可以实现一个可变电阻器来修改值来补偿温度。 泄漏部件可以包括允许电压通过的电容器配置。

公开(公告)号：US20090129172A1

公开(公告)日：2009-05-21

申请号：US11942526

申请日：2007-11-19

申请人： Jinsook Kim ,  Nian Yang ,  Hung-Jen Lin ,  Sachit Chandra

发明人： Jinsook Kim ,  Nian Yang ,  Hung-Jen Lin ,  Sachit Chandra

IPC分类号： G11C7/10

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C16/24

摘要： Systems and/or methods that accessing data to/from a memory are presented. A memory component can employ an optimized buffer component that can provide a single precharge control signal to facilitate precharging a bitline(s), a y-decoder component(s), an input/output line(s), and/or other lines or components associated with a buffer cell(s) in the optimized buffer component to facilitate optimized timing control associated with execution of operations to facilitate reducing errors that can be caused by charge sharing problems. The optimized buffer component can include an x-decoder component that can employ a JIT power component that can facilitate enabling a wordline associated with a buffer cell(s) only for the length of time access to the buffer cell is desired to read data therefrom or write data thereto to facilitate minimizing the access time and thereby minimize power consumption and/or thermal loading.

摘要翻译： 提供了访问/从存储器访问数据的系统和/或方法。 存储器组件可以使用优化的缓冲器组件，其可以提供单个预充电控制信号，以便于对位线，y解码器组件，输入/输出线和/或其他线路进行预充电，或者 与优化的缓冲器组件中的缓冲器单元相关联的组件，以促进与执行操作相关联的优化的定时控制，以便于减少可能由电荷共享问题引起的错误。 优化的缓冲器组件可以包括可以使用JIT功率组件的x解码器组件，该组件可以有助于实现与缓冲器单元相关联的字线，仅在长度时间内访问缓冲器单元才能从其读取数据， 向其写入数据以便于最小化访问时间，从而最小化功耗和/或热负载。

公开(公告)号：US07460415B2

公开(公告)日：2008-12-02

申请号：US11639936

申请日：2006-12-15

申请人： Yonggang Wu ,  Nian Yang ,  Tien-Chun Yang

发明人： Yonggang Wu ,  Nian Yang ,  Tien-Chun Yang

IPC分类号： G11C5/14

CPC分类号： G11C7/16 ,  G11C5/147 ,  G11C7/12

摘要： A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.

摘要翻译： 电压调节器包括减轻编程电压（VPROG）变化的电阻元件。 特别地，电阻允许电压调节器的副本在半导体衬底上更一致地制造。 因此，减轻了施加到存储器装置的不同位线的各个编程电压的变化。 随着越来越多的设备按需要执行，这减轻了产量损失，因此需要更少的丢弃物。

公开(公告)号：US07433228B2

公开(公告)日：2008-10-07

申请号：US11229519

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Hounien Chen ,  Sachit Chandra ,  Nian Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/10

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element having at least two charge storage areas for storing at least two independent charges, a source region and a drain region. The method includes designating at least one memory cell as a high-speed memory cell and pre-conditioning the high-speed memory cells by placing a first of the at least two charge storage areas into a programmed state, and subsequently enabling the programming on the second area with much higher rate.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储器单元包括衬底，控制栅极，具有用于存储至少两个独立电荷的至少两个电荷存储区域的电荷存储元件，源 区域和漏极区域。 该方法包括将至少一个存储器单元指定为高速存储单元，并且通过将至少两个电荷存储区域中的第一个置于编程状态来预处理高速存储器单元，并且随后使能在 第二个地区的利率要高得多。

公开(公告)号：US07345916B2

公开(公告)日：2008-03-18

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US20070291550A1

公开(公告)日：2007-12-20

申请号：US11423638

申请日：2006-06-12

申请人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

发明人： Nian Yang ,  Boon-Aik Ang ,  Yonggang Wu ,  Guowei Wang ,  Fan Wan Lai

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G11C7/00 ,  G11C16/06

CPC分类号： G11C7/1039 ,  G11C8/08 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/30 ,  G11C2207/2245

摘要： A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells (200) of a semiconductor memory device (100). A high voltage generator (106) during program or erase operations provides a continuous high voltage level (702) on selected word lines (502) and maintains a continuous high voltage level supply to a bit line decoder (120) which sequentially provides the high voltage level (706) to a first portion of bit lines (504) and discharges (708) those bit lines (504) before providing the high voltage level to a second portion (710).For additional improvements to program operations, the high voltage generator (106) decouples high voltages provided to the word lines (502) and the bit lines (504) by providing a current flow control device (1208) therebetween and provides a boosting voltage at a time (1104) to overcome a voltage level drop (1102) resulting from a capacitor load associated with selected bit lines (504) and/or the bit line decoder (120) precharges (1716) a second portion of the bit lines (504) while providing a high voltage level to a first portion to program (1706) a first portion of memory cells (200).For improvements to read operations, whether dynamic reference cells (2002) are blank is determined by providing non-identically regulated high voltage levels from a first voltage source (2112) to the dynamic reference cells (2002) and from a second voltage source (2104) to static reference cells (2004) and, if the dynamic reference cells (2002) are not blank, reads selected memory cells (200) by providing identically regulated high voltage levels to the selected memory cells (200), the dynamic reference cells (2002) and the static reference cells (2004).

公开(公告)号：US07196938B1

公开(公告)日：2007-03-27

申请号：US11229530

申请日：2005-09-20

申请人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

发明人： Yonggang Wu ,  Guowei Wang ,  Nian Yang ,  Aaron Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A non-volatile memory cell array, such as a Flash NOR array, is programmed by applying voltages to bit lines that connect to memory cells in the memory cell array. A first bit line corresponding to a first memory cell in the memory array may be turned on to perform a first programming operation for the first memory cell and second bit line corresponding to a second memory cell in the memory array may be turned on to perform a second programming operation that is configured to complete after the first programming operation. The turning on/off of the first and second bit lines may be overlapped to share charge between the first and second bit lines. This overlapping can reduce wasted power and decrease programming pulse overshoot problems.

摘要翻译： 诸如闪存NOR阵列的非易失性存储单元阵列通过将电压施加到连接到存储单元阵列中的存储单元的位线来编程。 对应于存储器阵列中的第一存储器单元的第一位线可以被接通以对第一存储器单元执行第一编程操作，并且可以打开与存储器阵列中的第二存储器单元相对应的第二位线来执行 第二编程操作被配置为在第一编程操作之后完成。 第一和第二位线的导通/截止可以重叠以在第一和第二位线之间共享电荷。 这种重叠可以减少浪费的功率并减少编程脉冲过冲问题。

公开(公告)号：US20070064464A1

公开(公告)日：2007-03-22

申请号：US11229527

申请日：2005-09-20

申请人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

发明人： Tiao-Hua Kuo ,  Nancy Leong ,  Nian Yang ,  Guowei Wang ,  Aaron Lee ,  Sachit Chandra ,  Michael VanBuskirk ,  Johnny Chen ,  Darlene Hamilton ,  Binh Le

IPC分类号： G11C17/00

CPC分类号： G11C5/147 ,  G11C16/12

摘要： A method is provided for programming a nonvolatile memory array including an array of memory cells, where each memory cell including a substrate, a control gate, a charge storage element, a source region and a drain region. The method includes receiving a programming window containing a predetermined number of bits that are to be programmed in the array and determining which of the predetermined number of bits are to be programmed in the memory array. The predetermined number of bits are simultaneously programmed to corresponding memory cells in the array. A programming state of the predetermined number of bits in the array is simultaneously verified.

摘要翻译： 提供了一种用于对包括存储器单元阵列的非易失性存储器阵列进行编程的方法，其中每个存储单元包括衬底，控制栅极，电荷存储元件，源极区域和漏极区域。 该方法包括接收包含要在阵列中被编程的预定数量的位的编程窗口，并且确定在存储器阵列中哪个预定位数被编程。 预定数量的位同时被编程到阵列中的对应存储器单元。 同时验证阵列中预定位数的编程状态。

公开(公告)号：US06734080B1

公开(公告)日：2004-05-11

申请号：US10159078

申请日：2002-05-31

申请人： Nian Yang ,  John Jianshi Wang ,  Tien-Chun Yang

发明人： Nian Yang ,  John Jianshi Wang ,  Tien-Chun Yang

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.

摘要翻译： 介绍了半导体隔离材料沉积系统及其方法，便于实现隔离区域的多步沉积。 在本发明的一个实施例中，集成电路包括密集配置的组件区域和稀疏配置的组件区域。 产生晶片中的有效区域并形成浅沟槽空间。 TEOS隔离材料层的薄层沉积在有源区域和浅沟槽的顶部。 例如，薄层的TEOS隔离材料层的厚度在下面有效区域顶部的4000至5000埃的范围内。 在TEOS隔离材料的薄层上进行反掩模和预平面化蚀刻。 在密集配置的部件区域和稀疏构造的部件区域之间的剩余的TEOS边缘尖峰是最小的（例如，约500埃），使用化学机械抛光工艺去除剩余的多余的氧化剂和氮化硅。在一个示例性实施方式中， 通过考虑一个工艺步骤对另一个工艺步骤的影响，可以获得成功的高产量结果的STI制造工艺的综合方法。

公开(公告)号：US06734028B1

公开(公告)日：2004-05-11

申请号：US10113152

申请日：2002-03-28

申请人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

发明人： Tien-Chun Yang ,  Nian Yang ,  Hyeon-Seag Kim

IPC分类号： H01L2166

CPC分类号： H01L22/34 ,  G01R31/275 ,  G01R31/2831

摘要： A method and apparatus for testing semiconductors comprising shallow trench isolation (STI) edge structures. An edge intensive shallow trench isolation structure (500) is coupled to a voltage source (310) and a current versus voltage profile is recorded. A planar structure (600) on the same wafer is coupled to a voltage source and a current versus voltage profile is recorded. An electrical stress is applied to both structures. Additional current profiles of each structure are obtained after the electrical stress. A comparison of difference current profiles obtained for the two types of structures may indicate the presence and/or the extent of STI corner effects. More specifically, a value for a normalized gate current difference for an STI edge intensive structure (500) greater than normalized gate current difference of a planar structure (600) is indicative of an increased rate of electron trapping in STI corners, which may indicate that the STI corners are too thin. In this novel manner, STI corner thickness may be observed in a non-destructive, electrical test process, resulting in higher quality and greater reliability of semiconductors using STI processes.

摘要翻译： 一种用于测试包括浅沟槽隔离（STI）边缘结构的半导体的方法和装置。 边缘密集的浅沟槽隔离结构（500）耦合到电压源（310），并记录电流对电压曲线。 在同一晶片上的平面结构（600）被耦合到电压源并且记录电流对电压曲线。 对两个结构都施加电应力。 在电应力之后，获得每个结构的附加电流分布。 对于两种类型的结构获得的差异电流曲线的比较可以指示STI拐角效应的存在和/或程度。 更具体地，大于平面结构（600）的归一化栅极电流差的STI边缘强化结构（500）的归一化栅极电流差的值表示STI拐角中的电子捕获速率增加，这可以指示 STI角落太薄了。 以这种新颖的方式，可以在非破坏性电气测试过程中观察到STI拐角厚度，从而导致使用STI工艺的半导体的更高质量和更高的可靠性。