公开(公告)号：US20210314202A1

公开(公告)日：2021-10-07

申请号：US17129799

申请日：2020-12-21

Applicant: Faraday Technology Corp.

Inventor： Shih-Yi Shih

IPC: H04L27/14 ,  H04L27/12 ,  H04L12/26 ,  H03M13/25

Abstract: The present invention discloses a Trellis-Coded-Modulation (TCM) decoder applied in a receiver, wherein the TCM decoder includes a branch metric unit, a path metric unit, a trace-back length selection circuit and a survival path management circuit. In operations of the TCM decoder, the branch metric unit is configured to receive multiple input codes to generate multiple sets of branch information. The path metric unit is configured to calculate multiple survival paths according to the multiple sets of branch information. The trace-back length selection circuit is configured to select a trace-back length, wherein the trace-back length is determined according to a signal quality of the receiver. The survival path management circuit is configured to return the multiple survival paths for the trace-back length in order to generate an output code.

公开(公告)号：US20210305990A1

公开(公告)日：2021-09-30

申请号：US17151673

申请日：2021-01-19

Applicant: FARADAY TECHNOLOGY CORPORATION ,  Faraday Technology Corp.

Inventor： Feng Xu ,  Chih-Yuan Hung ,  MENG ZHAO

IPC: H03M1/06

Abstract: A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

公开(公告)号：US20210304964A1

公开(公告)日：2021-09-30

申请号：US16942710

申请日：2020-07-29

Applicant: Faraday Technology Corp.

Inventor： Chia-Hui Tien ,  Tung-Tse Lin ,  Chih-Yuan Hung ,  Chih-Shiun Lu

IPC: H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01L49/02

Abstract: A capacitor includes a solid conductive plate, a first electrode, and a second electrode. The solid conductive plate is disposed above a substrate of a wafer. The solid conductive plate serves as a bottom plate of the capacitor. The first electrode is disposed above the solid conductive plate so that the solid conductive plate is located between the substrate and the first electrode. This first electrode serves as a top plate of the capacitor. The second electrode is disposed above the solid conductive plate, and is disposed beside the first electrode. The second electrode is electrically connected to the solid conductive plate.

公开(公告)号：US11070351B1

公开(公告)日：2021-07-20

申请号：US17138910

申请日：2020-12-31

Applicant: Faraday Technology Corp.

Inventor： Raghu Nandan Chepuri

IPC: H04L7/00 ,  H04L25/03 ,  H04L25/49

Abstract: The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.

公开(公告)号：US10797683B1

公开(公告)日：2020-10-06

申请号：US16811371

申请日：2020-03-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain ,  Chi-Yeu Chao ,  Prateek Kumar Goyal ,  Han-Kyul Lim

IPC: H03K3/017 ,  H03K5/156 ,  G06F1/04

Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.

公开(公告)号：US20200242058A1

公开(公告)日：2020-07-30

申请号：US16429070

申请日：2019-06-03

Applicant: Faraday Technology Corp.

Inventor： Shih-Ching Lin ,  Chun-Yuan Lai

IPC: G06F13/24 ,  G06F13/16

Abstract: An interrupt management system and a management method thereof are provided. The interrupt management system includes a processor and an interrupt signal expanding controller. The processor receives a plurality of original interrupt signals. The interrupt signal expanding controller includes a decoder and an interrupt vector table. The decoder receives a plurality of expanding interrupt request signals, and decodes the expanding interrupt request signals to generate the original interrupt signals, where number of the expanding interrupt request signals is larger than number of the original interrupt signals. The interrupt vector table stores a plurality of interrupt vectors. The decoder reads one of the interrupt vectors to obtain an accessed interrupt vector according to the expanding interrupt request signals, and the interrupt signal expanding controller transmits the accessed interrupt vector to the processor.

公开(公告)号：US10565381B2

公开(公告)日：2020-02-18

申请号：US16011650

申请日：2018-06-19

Applicant: Faraday Technology Corp.

Inventor： Chun-Yuan Lai ,  Chen-Chun Huang

IPC: G06F21/57 ,  G06F21/60 ,  G06F21/73 ,  G06F21/76 ,  G06F8/30 ,  G06F8/65 ,  G06F8/71

Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided. The method includes: utilizing an integrated circuit (IC) programmer to generate a seed file including characteristic information of the IC programmer; utilizing an encoder to encrypt original data representing a program code at least according to the characteristic information, to generate an encryption version of the original data; utilizing the IC programmer to decrypt the encryption version of the original data according to the characteristic information, to generate the original data utilizing the IC programmer to encrypt the original data at least according to predetermined information, to generate another encryption version of the original data; utilizing the microcontroller chip to decrypt the other encryption version at least according to predetermined information stored in the microcontroller chip to generate the original data, and write the original data into a non-volatile (NV) memory.

公开(公告)号：US20190122986A1

公开(公告)日：2019-04-25

申请号：US15860669

申请日：2018-01-03

Applicant: Faraday Technology Corp.

Inventor： Yi-Yeh Yang ,  Wang-Chin Chen ,  Po-Chen Lo ,  Shang-Ru Lin ,  Jen-Hsing Lin ,  Jin-Cheng Chen

IPC: H01L23/528 ,  H01L23/50 ,  H01L23/00

Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.

公开(公告)号：US10268226B1

公开(公告)日：2019-04-23

申请号：US15925781

申请日：2018-03-20

Applicant: Faraday Technology Corp.

Inventor： Wei Wang ,  Xiao-Dong Fei

IPC: G05F3/22 ,  G05F3/30

Abstract: The disclosure provides a voltage generating device and a calibrating method thereof. The voltage generating device includes a bandgap circuit, a regulator circuit and a calibrating circuit. The bandgap circuit provides a bandgap voltage. The regulator circuit generates an output voltage correspondingly according to the bandgap voltage. In a first stage of a calibration period, the calibrating circuit detects the bandgap voltage, and correspondingly sets a resistance of at least one resistor of the bandgap circuit according to the bandgap voltage. In a second stage of the calibration period, the calibrating circuit detects the output voltage, and correspondingly sets a resistance of at least one resistor of the regulator circuit according to the output voltage.

公开(公告)号：US10027330B1

公开(公告)日：2018-07-17

申请号：US15889740

申请日：2018-02-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Zhao-Yong Zhang ,  Shih-Chin Lin ,  Wei-Chang Wang

IPC: H03K19/20 ,  G06F17/50

Abstract: An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.