公开(公告)号：US07937258B2

公开(公告)日：2011-05-03

申请号：US12491106

申请日：2009-06-24

Applicant: Alexandre Birguer

Inventor： Alexandre Birguer

IPC: G06F9/455

CPC classification number: G06F12/1072 ,  G06F17/5027

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract translation: 一种用于在不同的存储器系统之间提供紧密映射的存储器映射系统以及用于制造和使用它们的方法。 存储器映射系统可以将内容从一个或多个第一存储器系统紧凑地映射到第二存储器系统中，而不会损失第二存储器系统中的存储器空间。 有利地，存储器映射系统可以应用于硬件仿真器存储器系统，以在编译期间将设计存储器系统更有效地映射到仿真存储器系统中。

公开(公告)号：US07640155B2

公开(公告)日：2009-12-29

申请号：US11141599

申请日：2005-05-31

Applicant: Mitchell G. Poplack ,  John A. Maher

Inventor： Mitchell G. Poplack ,  John A. Maher

IPC: G06F17/50 ,  G06F9/455 ,  G06F12/00 ,  G06F15/76 ,  G06F11/00 ,  G06F9/45

CPC classification number: G06F17/5027

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

Abstract translation: 用于连接通信系统的选定组件的目标接口系统及其制造和使用方法。 目标接口系统包括分布在多个可重新配置的逻辑设备中的目标接口逻辑。 通过串行链路耦合，可重配置逻辑器件每个都具有用于接收输入数据分组的输入连接和用于提供输出数据分组的输出连接。 串行链路将连续的可重构逻辑设备的输入和输出连接耦合以形成用于在可重新配置的逻辑设备之间分配数据分组的数据结构。 因此，数据结构维持可重构逻辑设备之间的数据同步，使得可重构逻辑设备中的目标接口逻辑的分布对于软件是透明的。

公开(公告)号：US07555423B2

公开(公告)日：2009-06-30

申请号：US11321201

申请日：2005-12-29

Applicant: William F. Beausoleil ,  Mitchell G. Poplack ,  Steven T Comfort ,  Beshara Elmufdi

Inventor： William F. Beausoleil ,  Mitchell G. Poplack ,  Steven T Comfort ,  Beshara Elmufdi

IPC: G06F9/455 ,  G06F9/45

CPC classification number: G06F17/5022 ,  G06F2217/86

Abstract: The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

Abstract translation: 本系统和方法涉及在软件驱动的硬件设计验证系统中包括仿真处理器的仿真处理器群集的互连。 处理器每个输出一个NBO输出信号。 通过将公共NBO总线划分成多个较小的NBO总线来互连这些簇，每个NBO总线具有独特的NBO信号，但是一起携带每个NBO。 每个较小的NBO总线被传递到一系列多路复用器，每个多路复用器专用于特定的处理器。 多路复用器选择一个信号以输出回仿真集群。 处理这些较小的NBO总线的多路复用器比先前所要求的窄，从而减少了多路复用器阵列和专用互连所需的功率，互连和面积。

公开(公告)号：US07440866B2

公开(公告)日：2008-10-21

申请号：US11140722

申请日：2005-05-31

Applicant: John A. Maher ,  Mitchell Grant Poplack

Inventor： John A. Maher ,  Mitchell Grant Poplack

IPC: G06F19/00 ,  G01R27/28 ,  G01R31/00 ,  G01R31/14

CPC classification number: G06F13/387

Abstract: A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads a selected image associated with a desired input/output technology prior to runtime. The selected image identifies an appropriate output driver supply voltage, and any auxiliary voltages are controlled as functions of the output driver supply voltage to limit voltage inconsistencies. Defaulting each voltage to its least dangerous state when unprogrammed, the target interface system subsequently monitors the voltages, disabling the input/output connections if a problem is detected. The target interface system likewise detects when a selected system component is absent, unpowered, and/or wrongly powered and provides contention detection. Thereby, the target interface system can facilitate communication among the system components while inhibiting damage to the target interface system and/or the system components.

Abstract translation: 用于连接通信系统的选定组件的目标接口系统及其制造和使用方法。 可重新配置以支持广泛的常规输入/输出技术，目标接口系统在运行之前下载与所需输入/输出技术相关联的所选图像。 所选择的图像识别适当的输出驱动器电源电压，并且任何辅助电压被控制为输出驱动器电源电压的功能，以限制电压不一致。 当未编程时，将每个电压默认为最小危险状态，目标接口系统随后监视电压，如果检测到问题，则禁用输入/输出连接。 目标接口系统同样检测所选择的系统组件何时不存在，无电源和/或错误地供电并提供争用检测。 因此，目标接口系统可以促进系统组件之间的通信，同时抑制对目标接口系统和/或系统组件的损坏。

公开(公告)号：US07107203B1

公开(公告)日：2006-09-12

申请号：US09655595

申请日：2000-09-06

Applicant: William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

Inventor： William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5027

Abstract: A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each input pin is connected to a correspondingly identified output pin, except for the pair with the outputs reversed, which pair signifies the cable length.

Abstract translation: 通过反转电缆中的至少两个导体的端对端对应来确定已经使用几种可能的电缆长度中的哪一种的系统和方法。 选择不同的两个导体来识别相应的不同的电缆长度。 每个输入引脚连接到相应识别的输出引脚，除了反向输出的输出引脚之外，这对引脚指示电缆长度。

公开(公告)号：US20060190237A1

公开(公告)日：2006-08-24

申请号：US11321201

申请日：2005-12-29

Applicant: William Beausoleil ,  Mitchell Poplack ,  Steven Comfort ,  Beshara Elmufdi

Inventor： William Beausoleil ,  Mitchell Poplack ,  Steven Comfort ,  Beshara Elmufdi

IPC: G06F9/455

CPC classification number: G06F17/5022 ,  G06F2217/86

Abstract: The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

公开(公告)号：US06901359B1

公开(公告)日：2005-05-31

申请号：US09656541

申请日：2000-09-06

Applicant: William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

Inventor： William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

IPC: G06F9/455 ,  G06F12/00 ,  G06F12/14 ,  G06F13/16 ,  G06F15/00 ,  G06F15/76 ,  G06F17/50

CPC classification number: G06F13/1615 ,  G06F17/5027

Abstract: A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one every clock cycle. When the memory controller detects transfer of the boundary of a predetermined number of clock cycles or words (e.g. 64 words or four clock cycles) the burst mode of data transfer is stopped and the memory controller waits for a “done” signal before resuming another cycle of the burst transfer mode. The memory controller on detecting a request on this address boundary first does a memory refresh followed by a requested operation; e.g. a continuation of the transfer operation.

Abstract translation: 用于批量传输到SRAM的系统和方法，其中开始存储器地址被锁存，然后每个时钟周期递增，以产生新的存储器地址。 地址被解码，并且存储器请求被流水线到SRAM存储器，每个时钟周期一个。 当存储器控制器检测到预定数量的时钟周期或字（例如64字或四个时钟周期）的边界的传送时，数据传输的突发模式被停止，并且存储器控制器在恢复另一个周期之前等待“完成”信号 的突发传输模式。 存储器控制器在该地址边界上检测请求首先进行存储器刷新，然后进行所请求的操作; 例如 转移操作的延续。

公开(公告)号：US06850880B1

公开(公告)日：2005-02-01

申请号：US09656147

申请日：2000-09-06

Applicant: William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

Inventor： William F. Beausoleil ,  R. Bryan Cook ,  Tak-kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  Lawrence A. Thomas ,  Norton J. Tomassetti

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5027

Abstract: A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses.

Abstract translation: 软件驱动的仿真器具有维护总线操作协议模式，其中在初始地址相位之后，通过自动递增发送和接收地址来连续流式传输数据。

公开(公告)号：US20020161568A1

公开(公告)日：2002-10-31

申请号：US09922113

申请日：2001-08-02

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

公开(公告)号：US20020095649A1

公开(公告)日：2002-07-18

申请号：US09949006

申请日：2001-09-06

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. Butts

IPC: G06F017/50

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

Abstract translation: 用于集成电路仿真和原型设计的逻辑芯片。 逻辑芯片包括多个逻辑元件，其被分成多个逻辑元件子集。 逻辑芯片还包括多个第一级互连。 多个第一级互连互连多个逻辑元件子集中的一个，从而形成多个第一级逻辑单元。 多个第一级逻辑单元被分成多个第一级逻辑单元子集。 逻辑芯片还包括多个第二级互连。 第二级互连将第一级逻辑单元的多个子集中的一个互连，从而形成多个第二级逻辑单元。 逻辑芯片还包括第三级互连。 第三级互连将多个第二级逻辑单元互连，从而形成第三级逻辑