公开(公告)号：US07307452B2

公开(公告)日：2007-12-11

申请号：US11258616

申请日：2005-10-25

Applicant: Nitin Deshmukh ,  Kailash Digari

Inventor： Nitin Deshmukh ,  Kailash Digari

IPC: H01L25/00 ,  H03K19/177

CPC classification number: H03K19/17736

Abstract: An interconnect structure enables indirect routing in programmable logic. The structure includes a plurality of routing lines, and switch box(es) and connection boxes coupled to the plurality of routing lines. The connection boxes include at least one programmable switch in each routing track. The position of the programmable switch(es) in each connection box connected to same interconnect matrix differs from the position of said programmable switch(es) in corresponding routing tracks of other connection boxes thereby utilizing the connectivity of said switch box for input connections and increasing the flexibility of connections.

Abstract translation: 互连结构可实现可编程逻辑中的间接路由。 该结构包括多个路由线路，以及耦合到多个路由线路的交换机盒和连接盒。 连接箱包括每个路由轨道中的至少一个可编程开关。 连接到相同互连矩阵的每个连接盒中的可编程开关的位置与其他连接盒的相应路线轨迹中的所述可编程开关的位置不同，从而利用所述开关盒的连接用于输入连接并增加 连接的灵活性。

公开(公告)号：US07283068B2

公开(公告)日：2007-10-16

申请号：US10615601

申请日：2003-07-07

Applicant: Abhishek Lal

Inventor： Abhishek Lal

IPC: H03M7/00

CPC classification number: H03M7/16

Abstract: An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

Abstract translation: 一种改进的二进制解码器，其包括激活对应于输入二进制值的所选输出的选择电路，以及耦合到每个输出的取消选择电路，当所选择的输出被激活时，其去激活所有其它输出。 取消选择电路装置具有连接到所选择的输出的单个输入和多个输出，每个输出连接到剩余输出中的一个，并且每当选择的输出被激活时迫使它们处于非活动状态。

公开(公告)号：US07271616B2

公开(公告)日：2007-09-18

申请号：US11190509

申请日：2005-07-26

Applicant: Ashish Kumar Goel ,  Davinder Aggarwal

Inventor： Ashish Kumar Goel ,  Davinder Aggarwal

IPC: G06F7/38 ,  H03K19/173

CPC classification number: H03K19/17764 ,  H03K19/17736

Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.

Abstract translation: 用于减小现场可编程门阵列（FPGA）中的回读时间的改进的数字电路包括具有多个锁存器的移位寄存器和提供给锁存器的时钟和复位信号。 在移位寄存器的每对锁存器之间提供互连电路，用于从期望的锁存器或锁存器提供选择性数据帧。 将控制信号发生器连接到所述互连电路的控制输入端可以快速回读所选择的数据帧，从而减少调试FPGA所花费的时间。

公开(公告)号：US20070210838A1

公开(公告)日：2007-09-13

申请号：US11683855

申请日：2007-03-08

Applicant: Ranjeet GUPTA ,  Abhishek KATIYAR

Inventor： Ranjeet GUPTA ,  Abhishek KATIYAR

IPC: H03B1/00

CPC classification number: H03K19/018521 ,  H03K17/6872 ,  H03K19/00315

Abstract: A high voltage tolerant input buffer capable of operating across wide range of power supply, including low power supply voltages, dynamically controls the gate voltage of an NMOS pass transistor by sensing the incoming high voltage signal at the pad and dynamically controlling the gate bias voltage of NMOS pass transistor.

Abstract translation: 能够在宽范围的电源（包括低电源电压）下工作的高耐压输入缓冲器通过感测焊盘上的输入高电压信号来动态地控制NMOS传输晶体管的栅极电压，并动态地控制栅极偏置电压 NMOS传输晶体管。

公开(公告)号：US20070204096A1

公开(公告)日：2007-08-30

申请号：US11648125

申请日：2006-12-29

Applicant: Mahesh Chandra

Inventor： Mahesh Chandra

IPC: G06F12/06

CPC classification number: G06T1/60

Abstract: A memory architecture for image processing comprising a memory array having multiple multi-byte memory data paths of equal multi-byte data width, and a multiplexing structure connected to the output of the multiple multi-byte data paths, capable of selectively providing a multi-byte data path of a desired width containing a desired permutation of bytes chosen from one or more of the multiple data paths.

Abstract translation: 一种用于图像处理的存储器架构，包括具有多个多字节数据宽度的多个多字节存储器数据路径的存储器阵列，以及连接到多个多字节数据路径的输出的复用结构，能够选择性地提供多字节数据， 包含从多个数据路径中的一个或多个中选择的期望的字节排列的期望宽度的字节数据路径。

公开(公告)号：US20070194768A1

公开(公告)日：2007-08-23

申请号：US11604655

申请日：2006-11-27

Applicant: Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

Inventor： Nitin Bansal ,  Rupesh Khare ,  Amit Katyal

IPC: G05F1/573 ,  G05F3/16

CPC classification number: G05F1/573

Abstract: A linear regulator with an N-type pass transistor includes an over-current protection circuit. A current sink is used as an indicator for an over-current condition and is coupled to the output of the linear regulator. The indicator is coupled to a feedback logic circuit that controls the current through the output load. The over-current protection circuit extensively uses N-type devices for various components including the output driver stage in the circuit. This results in reduced area for the over-current protection circuit.

Abstract translation: 具有N型传输晶体管的线性稳压器包括过流保护电路。 电流吸收器用作过电流状态的指示器，并且耦合到线性稳压器的输出。 该指示器耦合到控制通过输出负载的电流的反馈逻辑电路。 过电流保护电路广泛地使用N型器件用于各种部件，包括电路中的输出驱动级。 这导致过流保护电路的面积减小。

公开(公告)号：US20070168621A1

公开(公告)日：2007-07-19

申请号：US11638320

申请日：2006-12-13

Applicant: Amit Taneja ,  Mahesh Chandra

Inventor： Amit Taneja ,  Mahesh Chandra

IPC: G06F13/28 ,  G06F12/00

CPC classification number: G06T1/60

Abstract: To provide a memory efficient method and system for statistical data accumulation and processing, data is divided into multiple data zones and divided into subgroups of memories. A separate memory bin is assigned for each of the subgroups, and this memory bin is shared between various two data zones in each subgroup for processing and accumulation. In this scheme, the histogram data in each location of the separate memory bin for the previously accumulated data zones is processed before updating the stored value for the data zone requiring data accumulation.

Abstract translation: 为了提供用于统计数据累积和处理的存储器有效的方法和系统，数据被分成多个数据区并被划分成存储器的子组。 为每个子组分配一个单独的内存箱，并且该内存仓在每个子组中的各个两个数据区域之间进行共享以进行处理和累加。 在该方案中，在更新需要数据累积的数据区的存储值之前，处理用于先前累积的数据区的单独存储器仓的每个位置中的直方图数据。

公开(公告)号：US20070165463A1

公开(公告)日：2007-07-19

申请号：US11617234

申请日：2006-12-28

Applicant: Nasim Ahmad

Inventor： Nasim Ahmad

IPC: G11C16/06 ,  G11C8/00 ,  G11C5/14 ,  G11C11/34

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C7/227 ,  G11C8/10

Abstract: A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and block B. Block A is composed of a cluster of N dummy cells in which data is written during write operation. The remaining cells in the dummy column together form block B which is meant for providing load for the dummy bit line. During a write operation, a dummy word line is generated to enable dummy memory cells of block A. The dummy bit line is then made to travel half the number of rows in the normal memory array and then made to return back. A dummy data is then written in all the dummy cells in block A. Simultaneously, a normal memory cell is also accessed and actual data is written into it. As soon as the writing operation is complete, a W-reset signal is generated to indicate successful completion of write operation. Recovery operation for the next cycle is then started.

Abstract translation: 提供了一种用于半导体存储器的自定时写入架构及其提供方法。 半导体存储器的核心区域包括正常存储单元阵列和虚拟列。 虚拟列由两个块块A和块B组成。块A由写入操作期间写入数据的N个虚拟单元的簇组成。 虚拟列中的剩余单元一起形成块B，其用于为虚拟位线提供负载。 在写入操作期间，生成伪字线以使得块A的虚拟存储器单元。然后使伪位线行进一般存储器阵列中的行数的一半，然后使其返回。 然后在块A中的所有虚拟单元中写入伪数据。同时，还访问正常存储单元，并将实际数据写入其中。 一旦写入操作完成，就产生一个W复位信号，以指示写操作成功完成。 然后开始下一个循环的恢复操作。

公开(公告)号：US20070103245A1

公开(公告)日：2007-05-10

申请号：US11582127

申请日：2006-10-17

Applicant: Vikas Manocha

Inventor： Vikas Manocha

IPC: H03K3/26

CPC classification number: H03L7/02 ,  G06F1/04 ,  H03K3/011

Abstract: To calibrate an oscillator for microcontroller chip operation, an RC circuit is coupled to the microcontroller circuitry and a voltage signal is applied to the capacitor for changing the voltage across the capacitor. The voltage value across the capacitor is measured and compared to an expected voltage value. Adjustments to the frequency of the clock signal generated by the oscillator are made in response to the comparison.

Abstract translation: 为了校准用于微控制器芯片操作的振荡器，RC电路耦合到微控制器电路，并且电压信号被施加到电容器以改变电容器两端的电压。 测量电容器两端的电压值，并将其与预期的电压值进行比较。 对振荡器产生的时钟信号的频率进行调整，以响应比较。

公开(公告)号：US07206919B2

公开(公告)日：2007-04-17

申请号：US10319436

申请日：2002-12-13

Applicant: Ashish Kumar Goel ,  Manish Agarwal

Inventor： Ashish Kumar Goel ,  Manish Agarwal

IPC: G06F12/00 ,  G06F13/00

CPC classification number: G06F17/5054

Abstract: A system and method for enabling rapid partial configuration of reconfigurable devices includes a configuration definition unit and a configuration loading unit. The configuration definition unit defines partial configuration requirements, and contains at least a starting address of configuration data for the partial reconfiguration, data size specifying the number of contiguous locations to be reconfigured, and desired configuration data corresponding to the contiguous locations. The configuration loading unit provides for loading the configuration data into the reconfigurable device according to the partial configuration requirements without providing commands corresponding to any addresses outside of said configuration requirements.

Abstract translation: 一种用于实现可重构设备的快速部分配置的系统和方法包括配置定义单元和配置加载单元。 配置定义单元定义部分配置要求，并且至少包含用于部分重配置的配置数据的起始地址，指定要重新配置的连续位置的数量的数据大小以及对应于相邻位置的期望配置数据。 配置加载单元提供根据部分配置要求将配置数据加载到可重新配置设备中，而不提供与所述配置要求之外的任何地址相对应的命令。