公开(公告)号：US07046097B2

公开(公告)日：2006-05-16

申请号：US11069368

申请日：2005-03-01

Applicant: Mike Kappes ,  Terje Gloerstad

Inventor： Mike Kappes ,  Terje Gloerstad

IPC: H03B5/20

CPC classification number: H03L7/00 ,  H03B2201/0208 ,  H03B2201/025 ,  H03K3/0231

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

公开(公告)号：US20050260959A1

公开(公告)日：2005-11-24

申请号：US10523382

申请日：2003-07-25

Applicant: Alan Chin Yeo ,  Kui Lim

Inventor： Alan Chin Yeo ,  Kui Lim

IPC: H04N5/60 ,  H03B1/00 ,  H03B5/12 ,  H03J7/08 ,  H04B1/16 ,  H04B1/18 ,  H04B1/26 ,  H04N5/46

CPC classification number: H03B5/1268 ,  H03B5/1206 ,  H03B5/1243 ,  H03B2201/025

Abstract: In a local oscillator for a tuning arrangement for both TV and FM signals there is substantial risk of parasitic oscillation. A special provision is disclosed for effectively reducing this risk. The special provision is a connection of a damping resistor (R1a) for suppressing parsitic oscillations between ground and a junction (J2) of a parallel LC resonator of the local oscillator.

Abstract translation: 在用于TV和FM信号的调谐装置的本地振荡器中，存在寄生振荡的巨大风险。 披露了一项特别规定来有效降低风险。 特别规定是用于抑制本地振荡器的并联LC谐振器的接地和结（J 2）之间的斜体振荡的阻尼电阻器（R1a）的连接。

公开(公告)号：US20050168297A1

公开(公告)日：2005-08-04

申请号：US11095117

申请日：2005-03-31

Applicant: Ramon Gomez

Inventor： Ramon Gomez

IPC: H03B1/00 ,  H03B5/12 ,  H03D7/18 ,  H03J5/24 ,  H03L7/00 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03B5/00

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

公开(公告)号：US20050104677A1

公开(公告)日：2005-05-19

申请号：US11019451

申请日：2004-12-23

Applicant: Ramon Gomez

Inventor： Ramon Gomez

IPC: H03B1/00 ,  H03B5/12 ,  H03D7/18 ,  H03J5/24 ,  H03L7/00 ,  H03L7/089 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18 ,  H03B5/00

CPC classification number: H03L7/00 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/005 ,  H03B2201/02 ,  H03B2201/0208 ,  H03B2201/025 ,  H03D7/165 ,  H03D7/18 ,  H03J5/244 ,  H03J2200/10 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL. The reference scale current is generated based on a PLL control that specifics certain PLL characteristics such as reference frequency, loop bandwidth, and loop damping. Therefore, the reference pump current can be efficiently optimized for changing PLL operating conditions, in addition to compensating for variable VCO gain.

公开(公告)号：US06876266B2

公开(公告)日：2005-04-05

申请号：US10443835

申请日：2003-05-23

Applicant: Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

Inventor： Yido Koo ,  Jeong-Woo Lee ,  Joonbae Park ,  Kyeongho Lee

IPC: H03B5/08 ,  H03B1/00 ,  H03B5/12 ,  H03L7/099 ,  H03B5/00

CPC classification number: H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1265 ,  H03B2201/025 ,  H03J2200/10

Abstract: A voltage-controlled oscillator including an active oscillator circuit, an inductor, and capacitive circuits is disclosed. The capacitive circuits are selectively turned on and off to control the frequency of the voltage-controlled oscillator. Particularly, the inductor and the capacitors in the capacitive circuits form LC circuits that provide feedback to the active oscillator circuit. To avoid damage to the switches in the capacitive circuits, the capacitive circuits further comprise resistors. The resistors can be configured in several different ways so that the voltage-controlled oscillator can have a high degree of reliability, and a wide tuning range with constant phase noise performance.

Abstract translation: 公开了一种包括有源振荡器电路，电感器和电容电路的压控振荡器。 电容电路选择性地导通和截止以控制压控振荡器的频率。 特别地，电容电路中的电感器和电容器形成LC电路，向有源振荡器电路提供反馈。 为了避免损坏电容电路中的开关，电容电路还包括电阻器。 电阻器可以以几种不同的方式配置，使得压控振荡器可以具有高可靠性，以及具有恒定相位噪声性能的宽调谐范围。

公开(公告)号：US06853272B1

公开(公告)日：2005-02-08

申请号：US10295221

申请日：2002-11-15

Applicant: Rodney Alan Hughes

Inventor： Rodney Alan Hughes

IPC: H01P1/15 ,  H03B1/00 ,  H03J3/18 ,  H03J3/20 ,  H03J5/12

CPC classification number: H03J3/20 ,  H01P1/15 ,  H03B2201/025 ,  H03J3/185 ,  H03J2200/10 ,  H03J2200/38

Abstract: A linear voltage controlled capacitance circuit is provided that includes a plurality of MOS varactor pairs. Each MOS varactor pair is operable to receive a first tuning voltage, a second tuning voltage, and a bias voltage unique to the MOS varactor pair. The capacitance circuit is operable to generate a positive tank node signal and a negative tank node signal based on the first and second tuning voltages and the bias voltages. A means to control voltage-to-capacitance gain is also provided to compensate for coarse tuning capacitance change.

Abstract translation: 提供了包括多个MOS变容二极管对的线性压控电容电路。 每个MOS变容二极管对可操作以接收第一调谐电压，第二调谐电压和MOS变容二极管对独有的偏置电压。 电容电路可操作以基于第一和第二调谐电压和偏置电压产生正的储罐结点信号和负罐结点信号。 还提供了一种控制电压 - 电容增益的手段来补偿粗调谐电容变化。

公开(公告)号：US20040053595A1

公开(公告)日：2004-03-18

申请号：US10372922

申请日：2003-02-26

Inventor： Jiro Shinbo ,  Hirotaka Oosawa ,  Noriyuki Kurakami ,  Masumi Kasahara ,  Robert Astle Henshaw

IPC: H04B001/26 ,  H04B007/00 ,  H04B015/00

CPC classification number: H03L7/10 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/025 ,  H03D3/008 ,  H03J1/005 ,  H03J2200/10 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/193

Abstract: A communication semiconductor integrated circuit has an oscillator circuit forming part of a transmission PLL circuit fabricated on a single semiconductor chip together with an oscillator circuit forming part of a reception PLL circuit and an oscillator circuit for an intermediate frequency. The oscillator circuit for the transmission PLL circuit is configured to be operable in a plurality of bands. The communication semiconductor integrated circuit also comprises a circuit for measuring the oscillating frequency of the oscillator circuit for the transmission PLL circuit, and a storage circuit for storing the result of measurement made by the measuring circuit. A band to be used by the oscillator circuit for the transmission PLL circuit is determined based on values for setting the oscillating frequencies of the oscillator circuit forming part of the reception PLL circuit and the intermediate frequency oscillator circuit, and the result of measurement stored in the storage circuit.

Abstract translation: 通信半导体集成电路具有形成在单个半导体芯片上的传输PLL电路的一部分的振荡器电路以及形成接收PLL电路的一部分的振荡器电路和用于中频的振荡器电路。 用于传输PLL电路的振荡器电路被配置为可在多个频带中操作。 通信半导体集成电路还包括用于测量用于传输PLL电路的振荡器电路的振荡频率的电路和用于存储由测量电路进行的测量结果的存储电路。 用于传输PLL电路的振荡电路使用的频带基于用于设置构成接收PLL电路和中频振荡器电路的一部分的振荡电路的振荡频率的值和存储在传输PLL电路中的测量结果的值来确定 存储电路。

公开(公告)号：US20030206070A1

公开(公告)日：2003-11-06

申请号：US10138027

申请日：2002-05-03

Inventor： David M. Pietruszynski ,  Douglas R. Frey

IPC: H03B005/32

CPC classification number: H03K3/0307 ,  H03B5/32 ,  H03B2201/025 ,  H03J2200/10 ,  H03L7/099

Abstract: A method of tuning a DCXO includes the step of providing a coarse tuning array and a fine tuning array of capacitors fabricated on the same integrated circuit die. The coarse array is adjusted until the difference between a desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array. A DCXO apparatus includes at least one integrated circuit segmented switched capacitor network providing a capacitance that is a nonmonotonic function of a composite input code. The segmented switched capacitor network includes parallel coupled binary weighted and thermometer coded switched capacitor networks for coarse and fine tuning, respectively.

Abstract translation: 调谐DCXO的方法包括提供在同一集成电路管芯上制造的粗调谐阵列和电容器的微调阵列的步骤。 调整粗阵列，直到期望频率和输出频率之间的差值对应于不大于微调阵列范围的一半的电容变化。 在一个实施例中，在调整粗调谐阵列之前，将微调阵列调整到中等范围。 DCXO装置包括至少一个集成电路分段的开关电容器网络，其提供作为复合输入代码的非单调功能的电容。 分段开关电容网络分别包括用于粗调和微调的并联耦合二进制加权和温度计编码的开关电容器网络。

公开(公告)号：US06639479B2

公开(公告)日：2003-10-28

申请号：US10052856

申请日：2002-01-18

Applicant: Mike Kappes ,  Terje Gloerstad

Inventor： Mike Kappes ,  Terje Gloerstad

IPC: H03B520

CPC classification number: H03L7/00 ,  H03B2201/0208 ,  H03B2201/025 ,  H03K3/0231

Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract translation: 可用作时钟的集成振荡器包括围绕RC时间常数振荡的电路，RC时间常数可调，以提供期望的振荡频率。 更具体地说，振荡器包括电容器阵列，其具有并联耦合的多个电容器，其中每个电容器可被选择性地包括在RC时间常数中或者选择性地被包括在其中。 不是将电容值设置为期望的电容值，而是用于调整时间常数的系统包括用于测量输出频率并将其与经认证的频率源进行比较的电路，其中通过从电容器阵列中添加或去除电容器来调整时间常数 直到内部时钟的频率与预期频率相匹配。

公开(公告)号：US20020171500A1

公开(公告)日：2002-11-21

申请号：US10134897

申请日：2002-04-29

Inventor： Eiichi Hasegawa ,  Kazuhisa Oyama

IPC: H03B001/00

CPC classification number: H03B5/06 ,  H03B2201/0208 ,  H03B2201/025

Abstract: To provide a voltage controlled oscillator having a large variable width of oscillation frequency while ensuring oscillation starting performance, a P-channel MOS transistor Tr is made ON by detecting that an oscillation signal is provided with a predetermined amplitude value and oscillating operation is shifted from an initial state to a steady state by a detecting circuit OPC and a capacitor CA is connected in series with a series circuit constituted by a crystal resonator XL and a varicap diode CV. In the initial state, a load capacitance is reduced to thereby cancel an amount of reducing conductance gm of an oscillation amplifying portion to correspond to operation of the crystal resonator by a low amplitude and negative resistance necessary for maintaining excellent oscillation starting performance is provided and in the steady state, a width of changing the oscillation frequency is enlarged by enhancing an effect of the varicap diode CV.

Abstract translation: 为了提供振荡频率可变宽度大的压控振荡器，同时确保振荡起动性能，通过检测到振荡信号被设置有预定的振幅值，使P沟道MOS晶体管Tr成为导通，并且振荡操作从 由检测电路OPC和电容器CA的初始状态稳定状态与由晶体谐振器XL和变容二极管CV构成的串联电路串联连接。 在初始状态下，减小负载电容从而抵消振荡放大部分的电导率gm的减小量，以便与振荡放电部分的运行相对应，并且保持优异的振荡开始性能所需的低振幅和负电阻，并且在 通过增加变容二极管CV的影响，稳定状态，改变振荡频率的宽度被扩大。