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公开(公告)号：US20210391864A1
公开(公告)日：2021-12-16
申请号：US16901814
申请日：2020-06-15
摘要： A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.
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72.发明授权公开(公告)号：US11201767B1
公开(公告)日：2021-12-14
申请号：US17330937
申请日：2021-05-26
摘要： Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.
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73.发明申请公开(公告)号：US20210359688A1
公开(公告)日：2021-11-18
申请号：US17185813
申请日：2021-02-25
发明人： Ki Hyun PYUN , Hee SooK PARK
摘要： A clock data recovery circuit includes a phase-locked loop circuit generating a multi-phase clock signal based on input data, the phase-locked loop circuit including a multi-rate phase detector being operable at an initial rate among a plurality of rates in an initial period; a lock detector generating a lock-enable signal by detecting a lock state of the phase-locked loop circuit; a dead zone calibration circuit determining an operational rate corresponding to a data rate of the input data among the plurality of rates in response to the lock-enable signal; and a digital block controlling the multi-rate phase detector to operate at the operational rate, and generating a calibration-enable signal. The dead zone calibration circuit determines whether the multi-phase clock signal is locked within a dead zone in response to the calibration-enable signal, and changes a phase of the multi-phase clock signal based on the multi-phase clock signal.
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公开(公告)号：US20210351908A1
公开(公告)日：2021-11-11
申请号：US17382935
申请日：2021-07-22
发明人： Hiroyuki KOBAYASHI
摘要： A clock and data recovery device of a memory system receives a multiplexed data signal obtained by multiplexing a plurality of data units, each of which is to be transmitted to one of a plurality of memories for storage therein, in an area corresponding to each memory in an amplitude direction and a time direction. The clock and data recovery device includes a clock generation circuit configured to generate a clock, and a data recovery circuit configured to execute phase synchronization with respect to a synchronization signal included in the multiplexed data signal using the generated clock and to recover one of the data units from the area corresponding to one of the memories, from the multiplexed data signal.
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公开(公告)号：US20210328592A1
公开(公告)日：2021-10-21
申请号：US17103895
申请日：2020-11-24
发明人： Pei Wei CHEN , Fang-Ren Liao , Po Huang Huang
摘要： When digital input data disappear temporarily, within a counting period of the counter and pulse generator, an output voltage of the voltage generator rises, a threshold detector compares the output voltage of the voltage generator with a plurality of threshold values to generate a plurality of comparison results, and a logic gate unit generates a control signal according to the comparison results, to a charge pump, so that the charge pump controls the voltage-controlled oscillator to accelerate or decelerate.
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公开(公告)号：US11139841B2
公开(公告)日：2021-10-05
申请号：US15733343
申请日：2018-12-11
发明人： Jooseok Lee , Woojae Lee , Daeyoung Lee
摘要： The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as long-term evolution (LTE). According to various embodiments of the present disclosure, an apparatus of a transmitter in a wireless communication system may include an oscillating circuit for providing an oscillating signal, and a radio frequency (RF) circuit for converting a frequency of a transmit signal using the oscillating signal, and transmitting the transmit signal. The oscillating circuit may generate a base oscillating signal of a differential signal form, by multiplying a first signal and a second signal which constitute the different signal, generate a first signal set from the first signal and a second signal set from the second signal, and generate a signal in which at least one harmonic component adjacent to an intended frequency component is suppressed using the first signal set and the second signal set.
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公开(公告)号：US11139816B2
公开(公告)日：2021-10-05
申请号：US16822025
申请日：2020-03-18
发明人： Jen-Chu Wu , Po-Min Cheng , Wun-Jian Su , Chia-Hui Yu
摘要： A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.
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公开(公告)号：US11115178B1
公开(公告)日：2021-09-07
申请号：US17099819
申请日：2020-11-17
发明人： Jia-Ning Lou
摘要： A clock and data recovery device includes a phase detector circuitry, an analog modulation circuitry, a serial-to-parallel converter circuit, a digital modulation circuitry, and an oscillator circuit. The phase detector circuitry detects a data signal according to first and second clock signals to generate an up signal and a down signal. The analog modulation circuitry generates a first adjustment signal according to the up signal and the down signal. The serial-to-parallel converter circuit generates a first control signal according to the up signal, and to generate a second control signal according to the down signal. The digital modulation circuitry generates a digital code according to the first and the second control signals, and to generate a second adjustment signal according to the digital code. The oscillator circuit generates the first and the second clock signals according to the first adjustment signal and the second adjustment signal.
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公开(公告)号：US20210273642A1
公开(公告)日：2021-09-02
申请号：US16822025
申请日：2020-03-18
发明人： Jen-Chu Wu , Po-Min Cheng , Wun-Jian Su , Chia-Hui Yu
摘要： A clock and data recovery circuit is disclosed. The clock and data recovery circuit includes a phase detection circuit, a first voting circuit, a low-pass filtering circuit and a phase interpolation circuit. The phase detection circuit is configured to receive a first signal and a clock signal and generate a phase signal. The first voting circuit is configured to charge at least one capacitance component according to the phase signal and generate a first voting signal according to a charging result. The low-pass filtering circuit is configured to generate a phase control signal according to the first voting signal. The phase interpolation circuit is configured to generate the clock signal according to the phase control signal.
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公开(公告)号：US11095293B1
公开(公告)日：2021-08-17
申请号：US17139584
申请日：2020-12-31
发明人： Debapriya Sahu , Rittu Sachdev
摘要： An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal.
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