公开(公告)号：US20180337698A1

公开(公告)日：2018-11-22

申请号：US16050603

申请日：2018-07-31

申请人： QUALCOMM Incorporated

发明人： Shih-Wei CHOU ,  Chulkyu LEE ,  Dhaval SEJPAL

IPC分类号： H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  G06F13/40 ,  H04B3/52

CPC分类号： H04L25/493 ,  H04L25/02 ,  H04L25/0276

摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level.

公开(公告)号：US20180234122A1

公开(公告)日：2018-08-16

申请号：US15950779

申请日：2018-04-11

申请人： QUALCOMM Incorporated

发明人： Shih-Wei Chou ,  Chulkyu Lee ,  Dhaval Sejpal

IPC分类号： H04B1/04 ,  H04L25/493 ,  H04L25/02 ,  H04B3/52 ,  G06F13/40

CPC分类号： H04B1/04 ,  G06F13/4072 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/493

摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. A first terminal of a plurality of terminals may be driven such that transistors are activated to couple the first terminal to first and second voltage levels. The first terminal may further be driven such that a dedicated transistor is activated to couple the first terminal to an intermediate voltage level. The dedicated transistor is activated based on a voltage level for driving a second terminal of the three terminals and a voltage level for driving a third terminal of the three terminals.

公开(公告)号：US09525574B1

公开(公告)日：2016-12-20

申请号：US14853067

申请日：2015-09-14

申请人： Raytheon Company

发明人： Gary M. Graceffo ,  Andrew Kowalevicz

IPC分类号： H04B1/69 ,  H04B1/707 ,  H04B1/713 ,  H04L25/493 ,  H04B1/04

CPC分类号： H04L25/493 ,  H04B1/0003 ,  H04B1/0475

摘要： Methods and apparatus for transmitting data at a varying effective data rate (EDR) at a constant baud rate by encoding the data prior to transmission with a sequence. In embodiments, the sequence comprises a pseudo random number sequence, Barker sequence, and/or other sequence. Embodiments of a receiver decode the data transmitted at a varying effective data rate (EDR) at a constant baud rate by encoding the data prior to transmission with a sequence.

摘要翻译： 用于以恒定波特率以变化的有效数据速率（EDR）发送数据的方法和装置，通过在用序列传输之前对数据进行编码。 在实施方案中，序列包含伪随机数序列，巴克序列和/或其他序列。 接收机的实施例通过在用序列传输之前对数据进行编码，以恒定的波特率来解码以变化的有效数据速率（EDR）发送的数据。

公开(公告)号：US09009335B2

公开(公告)日：2015-04-14

申请号：US14098783

申请日：2013-12-06

申请人： Sony Corporation

发明人： Gen Ichimura ,  Hidekazu Kikuchi ,  Yasuhisa Nakajima

IPC分类号： G06F11/00 ,  H04J3/06 ,  H04L25/02 ,  H04L25/493 ,  H04N21/436 ,  H04N21/4363 ,  H04N21/643 ,  H04L7/00

CPC分类号： H04L25/0276 ,  H04J3/0638 ,  H04J3/0641 ,  H04L7/0016 ,  H04L7/0091 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/493 ,  H04N21/43615 ,  H04N21/43635 ,  H04N21/64322

摘要： A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

摘要翻译： 视频信号和音频信号是从源设备传送到宿设备的TMDS。 通过与TMDS传输线分开提供的预留线路和HPD线路，双向传输以太网™信号，并且还将SPDIF信号从宿设备发送到源设备。 以太网™发送器/接收器电路之间双向传输的以太网™信号由放大器进行差分传输，由放大器接收。 来自SPDIF发送器电路的SPDIF信号是从加法器发送的共模信号，并被加法器接收以提供给SPDIF接收器电路。

公开(公告)号：US08941512B2

公开(公告)日：2015-01-27

申请号：US13555518

申请日：2012-07-23

申请人： Henry Markram

发明人： Henry Markram

IPC分类号： H03M7/00 ,  H04L25/493

CPC分类号： H04L25/493

摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for encoding and decoding information. In one aspect, methods of encoding information in an encoder include receiving a signal representing information using a collection of discrete digits, converting, by an encoder, the received signal into a time-based code, and outputting the time-based code. The time-based code is divided into time intervals. Each of the time intervals of the time-based code corresponds to a digit in the received signal. Each digit of a first state of the received signal is expressed as an event occurring at a first time within the corresponding time interval of the time-based code. Each digit of a second state of the received signal is expressed as an event occurring at a second time within the corresponding time intervals of the time-based code, the first time is distinguishable from the second time.

摘要翻译： 方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于对信息进行编码和解码。 在一个方面，编码器中信息编码的方法包括使用离散数字的集合接收表示信息的信号，由编码器将接收到的信号转换成基于时间的代码，并输出基于时间的代码。 基于时间的代码被分为时间间隔。 基于时间的代码的每个时间间隔对应于接收信号中的数字。 接收信号的第一状态的每个数字表示为在时间码的对应时间间隔内的第一时间发生的事件。 接收信号的第二状态的每个数字被表示为在时间码的对应时间间隔内的第二时间发生的事件，第一次与第二次可区分。

公开(公告)号：US20050134451A1

公开(公告)日：2005-06-23

申请号：US10867649

申请日：2004-06-16

申请人： Ari Nikkola

发明人： Ari Nikkola

IPC分类号： A61B5/00 ,  A61B5/02 ,  A61B5/021 ,  A61B5/024 ,  G08B1/08 ,  G08C20060101 ,  G08C17/00 ,  G08C17/02 ,  H04L25/493

CPC分类号： A61B5/0002 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/1112 ,  A61B5/681 ,  A61B2503/10 ,  A61B2560/0209

摘要： The invention relates to a method and apparatus in connection with a wristop computer. According to the method, a desired variable is measured using a measuring unit (1), the measured variable is equipped with at least one digital codeword (15) and transmitted wirelessly over a transfer channel (3) to a receiver (3), and at the other end of the transfer channel (3), the transmitter's (2) signal is identified on the basis of at least one codeword (15). According to the invention, the digital codeword (15) is transmitted to the receiver (3) together with the measured variable depicted as time-period data (t1 or t3).

摘要翻译： 本发明涉及一种与威力达计算机有关的方法和装置。 根据该方法，使用测量单元（1）测量期望的变量，测量的变量装备有至少一个数字码字（15），并通过传送信道（3）无线地传送到接收机（3），以及 在传输信道（3）的另一端，基于至少一个码字（15）识别发射机（2）信号。 根据本发明，数字码字（15）与作为时间段数据（t 1或t 3）所示的测量变量一起发送到接收机（3）。

公开(公告)号：US5952849A

公开(公告)日：1999-09-14

申请号：US805075

申请日：1997-02-21

申请人： Geoffrey T. Haigh

发明人： Geoffrey T. Haigh

IPC分类号： H04L25/02 ,  H04L25/493 ,  H03K19/0175

CPC分类号： H04L25/493 ,  H04L25/0266

摘要： A logic isolation circuit with high transient immunity has a link-coupled transformer assembly for providing isolation. An input circuit provides pulses that indicate rising and falling edges, and an output circuit on the isolated side of the barrier converts the signal with pulses back into a digital logic signal with rising and falling edges. An interrogation feature allows the output to be updated frequently. The logic isolator can be provided in a single module for use in a process control board, or it can be provided as multiple parts for mounting on a circuit board.

摘要翻译： 具有高瞬态抗扰度的逻辑隔离电路具有用于提供隔离的链路耦合变压器组件。 输入电路提供指示上升沿和下降沿的脉冲，并且在屏障的隔离侧的输出电路将具有脉冲的信号转换成具有上升沿和下降沿的数字逻辑信号。 询问功能允许频繁更新输出。 逻辑隔离器可以设置在用于过程控制板的单个模块中，或者可以被设置为用于安装在电路板上的多个部件。

公开(公告)号：US5793754A

公开(公告)日：1998-08-11

申请号：US623849

申请日：1996-03-29

申请人： John Houldsworth ,  Joseph Ingram Field, Jr. ,  Geoffrey Bollinger Cox

发明人： John Houldsworth ,  Joseph Ingram Field, Jr. ,  Geoffrey Bollinger Cox

IPC分类号： H04B1/56 ,  H04B14/02 ,  H04L5/14 ,  H04L25/02 ,  H04L25/493

CPC分类号： H04B14/026 ,  H04L25/02 ,  H04L25/493 ,  H04L5/1469 ,  H04B1/56

摘要： A pulse density signaling input/output (PDSIO) scheme is implemented to provide a two-way, two-wire hybrid analog/digital communications system. PDSIO signals are sent as logic pulses from a "master" port to one or more "slave" ports over a twisted pair. From one to a predetermined maximum number of logic pulses are transmitted over two wires at baseband by a master port during a defined period. The modulation used by the master port is pulse density modulation at base band so that the transmitted signal appears to be a d.c. logic signal. The pulses transmitted to the slave port are also used to power the slave port. The slave port communicates with the master port over the same two wires using a pulsed current modulation that multiplexes data on the pulse signals from the master port.

摘要翻译： 实现脉冲密度信令输入/输出（PDSIO）方案来提供双向，双线混合模拟/数字通信系统。 PDSIO信号通过双绞线从“主”端口发送到一个或多个“从”端口的逻辑脉冲。 在一定时间内由主端口在一根到一条预定的最大数量的逻辑脉冲在基带上通过两根线发送。 主端口使用的调制是在基带处的脉冲密度调制，使得发送的信号看起来是直流。 逻辑信号。 传输到从端口的脉冲也用于为从站端口供电。 从端口通过使用脉冲电流调制在相同的两条线上与主端口通信，该脉冲电流调制复用来自主端口的脉冲信号的数据。

公开(公告)号：US5640160A

公开(公告)日：1997-06-17

申请号：US557347

申请日：1995-11-14

申请人： Kenichi Miwa

发明人： Kenichi Miwa

IPC分类号： H03M5/14 ,  H04B10/114 ,  H04B10/40 ,  H04B10/50 ,  H04B10/524 ,  H04B10/556 ,  H04B10/60 ,  H04L25/49 ,  H04L25/493 ,  H04N5/00 ,  H04Q1/39 ,  H03K7/04

CPC分类号： H04L25/493

摘要： A binary code is divided into 2-bit data units. Pulse position modulation is performed on each unit rather than on each bit. Since a pulse is not formed for each bit, the transmission interval and transmission frame interval for the modulated signal is shortened, thus enabling high speed transmission. Since the pulse interval of the signal contains the information of the 2-bit data unit, only the leading edge of the pulse needs to be detected. This feature allows reliable demodulation even under adverse conditions such as a long-distance transmission route or a noisy transmission route. Since there is no need to demodulate by comparing each bit with an immediately preceding bit, complex demodulation schemes and decoding registers are not needed on the receiving side. Since the width of the pulse does not contain any transmission information, the pulse width is made as short as possible, thereby reducing battery consumption within the transmitter.

摘要翻译： 二进制码分为2位数据单元。 在每个单元上执行脉冲位置调制，而不是在每个位上执行。 由于不对每个比特形成脉冲，所以调制信号的发送间隔和发送帧间隔缩短，能够实现高速发送。 由于信号的脉冲间隔包含2位数据单元的信息，因此只需要检测脉冲的前沿。 该特征即使在诸如长距离传输路由或噪声传输路由的不利条件下也可以进行可靠的解调。 由于不需要通过将每个比特与前一比特进行比较来解调，所以在接收侧不需要复杂的解调方案和解码寄存器。 由于脉冲的宽度不包含任何传输信息，所以使脉冲宽度尽可能的短，从而减少发射机内的电池消耗。

公开(公告)号：US5488628A

公开(公告)日：1996-01-30

申请号：US187320

申请日：1994-01-26

申请人： Pierre-Yves Thoulon

发明人： Pierre-Yves Thoulon

IPC分类号： H03M5/06 ,  H04L5/22 ,  H04L25/493 ,  H03K7/04

CPC分类号： H04L5/225 ,  H04L25/493

摘要： A known method for transition encoding a logic signal involves: recording for each of a succession of window periods, the position of occurence of a first transition of the logic signal during that window by noting a count value reached at the time the first transition occurs; indicating the status of the logic signal after this first transition by appropriately setting a first bit; and indicating the occurence of a second transition during the same window period by the setting of a second bit. In order to avoid wrong encodings resulting from the occurence of a third transition within the same window period, the present invention provides for the effect delaying of any such third transition until the start of the next window period.

摘要翻译： 用于转换编码逻辑信号的已知方法包括：通过记录在第一次转变发生时达到的计数值，记录窗口周期中的每一个，在该窗口期间逻辑信号的第一转换的发生位置; 通过适当地设置第一位来指示在该第一转换之后的逻辑信号的状态; 并且通过设置第二比特来指示在同一窗口周期期间发生第二次转换。 为了避免在同一窗口周期内发生第三次转换所导致的错误编码，本发明提供了任何这样的第三过渡的延迟直到下一个窗口周期的开始。