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公开(公告)号：US20210193198A1
公开(公告)日：2021-06-24
申请号：US16951705
申请日：2020-11-18
发明人： James Brian Johnson
摘要： Methods, systems, and devices for clock locking for frame-based communications of memory devices are described. A memory system may include a memory device and a host device. The memory device may receive one or more frames of data from the host device, the one or more frames of data communicated by the host device using a first frame clock. The memory device may generate a second frame clock aligned with the one or more frames on receiving the one or more frames and align one or more operations of the memory device with the second frame clock. In some examples, the host device may receive a second set of frames from the memory device based on transmitting the first set of frames. The host device may align one or more operations of the host device with the second set of frames received from the memory device.
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公开(公告)号：US20210191453A1
公开(公告)日：2021-06-24
申请号：US16736819
申请日：2020-01-08
发明人： Sheng-Wen Chen , Shih-Yang Sun , Zhen-Hong Hung
IPC分类号： G06F1/10 , G06F1/08 , G06F1/12 , G11C11/4076 , G11C11/4074 , H03L7/08
摘要： A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
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公开(公告)号：US20210191452A1
公开(公告)日：2021-06-24
申请号：US16723273
申请日：2019-12-20
申请人： Arm Limited
摘要： A monitoring system for monitoring delay of critical path timing margins can include a plurality of adaptive monitoring circuits, where each adaptive monitoring circuit is coupled to a corresponding one of a plurality of paths in a circuit. Each adaptive monitoring circuit can include a first delay element designed to cause a mean timing margin of the plurality of N paths in the circuit to be within one minimum mean unit delay; a second delay element coupled to the first delay element and designed to add a mean delay of k*σmax; a set-up capture element capturing an output of the second delay element; and a set-up warning comparison element that outputs a set-up warning signal when the output of the set-up capture element and a shadow capture element or a capture element of the corresponding one of the plurality of paths do not satisfy an expected condition.
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公开(公告)号：US11043946B1
公开(公告)日：2021-06-22
申请号：US16776776
申请日：2020-01-30
IPC分类号： H03K19/003 , G06F1/10 , H03K5/00
摘要： A method for adjusting a skew between a second clock signal and a first clock signal is provided. The second clock signal has been propagated from a first clock source through a second clock tree. The second clock tree comprises a programmable delay line that induces a delay. The method comprises at least one iteration of: measuring a skew between the second clock signal and the first clock signal, comparing an absolute difference of the measured skew and a sum of delay changes initiated in a time window preceding the measurement with a target skew, and initiating a delay change of the delay induced by the programmable delay line in the second clock tree depending on a result of the comparison.
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公开(公告)号：US20210181832A1
公开(公告)日：2021-06-17
申请号：US17247649
申请日：2020-12-18
申请人： Intel Corporation
发明人： Nausheen Ansari , Ziv Kabiry , Gal Yedidia
IPC分类号： G06F1/3296 , G06F3/14 , G06F1/10
摘要： In one embodiment, an apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link.
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公开(公告)号：US20210181783A1
公开(公告)日：2021-06-17
申请号：US17112853
申请日：2020-12-04
发明人： Giuseppe Cavallaro
摘要： An embodiment electronic system comprises a first device, a second device and a clock generator circuit. The clock generator circuit is configured to provide a clock signal having a selectable frequency. The first device comprises a first processing circuit having coupled therewith a first Ethernet interface, and the second electronic device comprises a second processing circuit having coupled therewith a second Ethernet interface. At least one of the first device and the second device is configured to determine a frequency of the clock signal as a function of an operating parameter of the first device and/or of the second device and/or as a function of a parameter of the frames exchanged between the first device and the second device, and to act on the clock generator circuit to operate the clock generator circuit at the frequency.
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公开(公告)号：US20210173428A1
公开(公告)日：2021-06-10
申请号：US16315924
申请日：2019-01-04
发明人： Yong LIU , Yueqiang CHENG , Jian OUYANG , Tao WEI
摘要： According to one embodiment, a DP accelerator includes one or more execution units (EUs) configured to perform data processing operations in response to an instruction received from a host system coupled over a bus. The DP accelerator includes a security unit (SU) configured to establish and maintain a secure channel with the host system to exchange commands and data associated with the data processing operations. The DP accelerator includes a time unit (TU) coupled to the security unit to provide timestamp services to the security unit, where the time unit includes a clock generator to generate clock signals locally without having to derive the clock signals from an external source. The TU includes a timestamp generator coupled to the clock generator to generate a timestamp based on the clock signals, and a power supply to provide power to the clock generator and the timestamp generator.
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公开(公告)号：US20210173427A1
公开(公告)日：2021-06-10
申请号：US17102119
申请日：2020-11-23
申请人： Rambus Inc.
发明人： Jun Kim , Pak Shing Chau , Wayne S. Richardson
摘要： A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.
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公开(公告)号：US20210165393A1
公开(公告)日：2021-06-03
申请号：US17165946
申请日：2021-02-03
发明人： Masaomi KUDO , Yu KATONO
IPC分类号： G05B19/418 , G06F1/10
摘要： A controller includes a port via which a control command is output to an industrial equipment at every control cycle, a clock configured to generate a control clock based on which the control cycle is generated, and a time counter configured to count a time counter value at every cycle that is equal to the control cycle.
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公开(公告)号：US11023176B2
公开(公告)日：2021-06-01
申请号：US16605135
申请日：2017-04-28
发明人： Jun Tu
摘要： The storage interface includes a first programmable input/output unit configured to perform phase inversion on a clock signal that is output by the master controller, and output the phase-inverted clock signal to the storage device. The storage interface includes a second programmable input/output unit configured to delay a data signal that is output by the master controller, and output the delayed data signal to the storage device, where the delayed data signal is delayed by a time ΔT relative to the clock signal that is output by the master controller, and TCLK/2−ΔT≥TISU and ΔT≥TIH, where TCLK represents a period of the clock signal, TISU represents a shortest input setup time required by the storage device in each of different data rate modes, and TIH represents a shortest input hold time employed by the storage device in each of different data rate modes.
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