公开(公告)号：US2962571A

公开(公告)日：1960-11-29

申请号：US74495458

申请日：1958-06-27

申请人： ALLIED CONTROL CO

发明人： MARTIN ZANICHKOWSKY

IPC分类号： H01H13/12 ,  H01H23/12

CPC分类号： H01H23/12 ,  H01H13/12

公开(公告)号：US2116656A

公开(公告)日：1938-05-10

申请号：US73578734

申请日：1934-07-18

申请人： HENRY DREYFUS

发明人： HENRY DREYFUS

IPC分类号： C07C51/56

CPC分类号： C07C51/56 ,  C07C53/12

公开(公告)号：US20020062323A1

公开(公告)日：2002-05-23

申请号：US09834429

申请日：2001-04-13

申请人： Yozan Inc

发明人： Sunao Takatori ,  Hisanori Kiyomatsu

IPC分类号： G06F007/00

CPC分类号： G06F16/951

摘要： A browser apparatus, a server apparatus, a computer-readable medium, a search system and a search method are provided which enable a user to readily execute a search on a network particularly even if the user is a computer illiterate. In other words, for instance, the browser apparatus, the server apparatus, the computer-readable medium, the search system and the search method of the present invention perform as follows: searching sites and/or pages on the network; obtaining the values of access counters in sites and/or pages found in the search; and arranging the sites and/or the pages found in the search in accordance with the obtained access counter values so that the site or the page having the larger access counter value is ranked higher, and for outputting the information on the arrangement of the sites and/or pages as the result of the search.

摘要翻译： 提供了浏览器装置，服务器装置，计算机可读介质，搜索系统和搜索方法，其使得用户即使用户是计算机文盲也能够容易地在网络上执行搜索。 换句话说，例如，本发明的浏览器装置，服务器装置，计算机可读介质，搜索系统和搜索方法执行如下：搜索网络上的站点和/或页面; 获取在搜索中找到的站点和/或页面中的访问计数器的值; 以及根据获得的访问计数器值排列在搜索中找到的站点和/或页面，使得具有较大访问计数器值的站点或页面排名较高，并且用于输出关于站点和 /或作为搜索结果的页面。

公开(公告)号：US20020052839A1

公开(公告)日：2002-05-02

申请号：US10001111

申请日：2001-11-02

申请人： Yozan, Inc.

发明人： Sunao Takatori

IPC分类号： G06F017/60

CPC分类号： G07G1/12 ,  G06Q20/00 ,  G06Q20/10 ,  G06Q20/102 ,  G06Q20/20 ,  G06Q20/32 ,  G06Q20/3227

摘要： A method of efficiently collecting a charge for the payment of money for an article of merchandise that are purchased is used in a charge collection system having a contactless storage medium in an article tag which has recorded product information therein, a contactless storage medium in a customer terminal which has recorded customer ID information therein, and a charging device in a store. The method comprises the steps of reading the product information from the contactless storage medium in the article tag into the charging device (step 71), calculating a total amount of money with the charging device based on the read product information (step 72), settling the payment of the calculated total amount of money with the charging device by receiving corresponding cash or reading the customer ID information from the contactless storage medium in the customer terminal (steps 74-78), and recording information of the settled payment in the contactless storage medium in the article tag (steps 79, 80).

摘要翻译： 一种有效地收取用于购买商品的货币的费用的方法被用在具有在其中记录了产品信息的物品标签中的非接触存储介质的计费收集系统中，在客户端中存储非接触式存储介质 其中记录了客户ID信息的终端，以及商店中的计费装置。 该方法包括以下步骤：将商品标签中的非接触式存储介质中的商品信息读入充电装置（步骤71），基于读取的商品信息计算与充电装置的总金额（步骤72），结算 通过接收相应的现金或从客户终端中的非接触式存储介质读取客户ID信息来支付与计费设备的计算总金额（步骤74-78），并将结算的支付信息记录在非接触式存储器 物品标签中的介质（步骤79,80）。

公开(公告)号：US6038250A

公开(公告)日：2000-03-14

申请号：US3509

申请日：1998-01-06

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou

IPC分类号： H04B1/707 ,  H04B1/7075 ,  H04B7/26 ,  H04W56/00 ,  H04W76/02 ,  H04B7/216

CPC分类号： H04B1/7077 ,  H04B1/7083 ,  H04B1/70735 ,  H04B1/70751 ,  H04B2201/70702

摘要： Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter and is correlated with a spread code supplied from a spread code generator. A signal electric power calculator calculates the electric power of the correlation output of the matched filter, and outputs the result to a long code synchronization timing determiner, a threshold value calculator, and a long code identifier. During the initial cell search, the spread code generator outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.

摘要翻译： 使用初始同步方法和用于DS-CDMA基站间异步蜂窝系统的接收机以高速搜索小区。 基带接收信号被输入到匹配滤波器，并与从扩展码发生器提供的扩展码相关。 信号电力计算器计算匹配滤波器的相关输出的功率，并将结果输出到长码同步定时确定器，阈值计算器和长码标识符。 在初始小区搜索期间，扩频码发生器输出每个基站的控制信道共同的短码＃0。 在确定了长代码同步定时之后，构成从每个基站唯一的长码#i合成的合成扩展码序列的一部分的N个码片的每个片段和短码＃0 顺序更换并输出。

公开(公告)号：US5959875A

公开(公告)日：1999-09-28

申请号：US812650

申请日：1997-03-07

申请人： Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

发明人： Nobuaki Kawahara ,  Kenzo Urabe ,  Changming Zhou ,  Guoliang Shou

IPC分类号： G06G7/19

CPC分类号： G06G7/1921

摘要： A signal characterizer for performing functional transformations such as Fast Fourier Transforms (FFTs), which converts an input serial analog signal into a plurality of parallel discrete signals using an analog-type serial-to-parallel converter. The discrete signals are then supplied to the input terminals of butterfly operation circuits to process the parallel discrete signals into a plurality of transformed signals. A switch supplies the transformed signals to a serial signal output terminal. The switch is controlled by a controller so that the input signal sequence is converted to a serial signal sequence according to a predetermined order.

摘要翻译： 一种用于执行诸如快速傅立叶变换（FFT）的功能变换的信号表征器，其使用模拟型串并转换器将输入的串行模拟信号转换为多个并行离散信号。 然后将离散信号提供给蝶形运算电路的输入端，以将并行离散信号处理成多个变换信号。 开关将变换的信号提供给串行信号输出端子。 开关由控制器控制，使得输入信号序列根据预定顺序被转换成串行信号序列。

公开(公告)号：US5917343A

公开(公告)日：1999-06-29

申请号：US922680

申请日：1997-09-03

申请人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H01L27/02 ,  H01L27/07 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0948 ,  H01L27/00

CPC分类号： H01L27/0705 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/092 ,  H03K19/00384 ,  H01L2924/0002

摘要： A MOS inverter within a large scale integrated circuit (LSI) includes a pair of circuits with the same performance. Each of the circuits includes a plurality of MOS inverters serially connected from the first stage to the last stage. Each of the MOS inverters is provided with an input such that the input of the MOS inverters of the first stage are formed to be adjacent one another.

摘要翻译： 大规模集成电路（LSI）中的MOS反相器包括具有相同性能的一对电路。 每个电路包括从第一级到最后级串联连接的多个MOS反相器。 每个MOS反相器具有输入，使得第一级的MOS反相器的输入形成为彼此相邻。

公开(公告)号：US5887024A

公开(公告)日：1999-03-23

申请号：US780145

申请日：1996-12-26

申请人： Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

发明人： Xiaoling Qin ,  Kunihiko Suzuki ,  Guoliang Shou ,  Changming Zhou ,  Jie Chen

IPC分类号： H03H11/04 ,  H03H17/02 ,  H04B15/00 ,  H04K1/00 ,  H04L27/30

CPC分类号： H03H11/04 ,  H03H17/02

摘要： The present invention provides a matched filter which can refresh an entire while keeping the speed of a calculation comparable to a small sized circuit. The first and second addition circuits of a matched filter of the present invention are classified into a plurality of groups, the first and second auxiliary adders replace functions for the groups of the first and second adders respectively. The outputs of the first and second adders are then inputted to the first and second subtractors, respectively, and the refreshing means appropriately refreshes the groups replaced by the first and second auxiliary adders. Further, the present invention decreases the number of auxiliary sapling and holding circuits to be used, and decides the refreshing intervals by considering the change of the voltage caused by leakage and other permissible errors of output voltage.

摘要翻译： 本发明提供了一种匹配滤波器，其可以保持与小尺寸电路相当的计算速度的整体刷新。 本发明的匹配滤波器的第一和第二加法电路分为多个组，第一和第二辅助加法器分别代替第一和第二加法器的组的功能。 然后，第一和第二加法器的输出分别输入到第一和第二减法器，并且刷新装置适当地刷新由第一和第二辅助加法器替换的组。 此外，本发明减少了要使用的辅助树苗和保持电路的数量，并且通过考虑由漏电引起的电压的变化和输出电压的其他允许误差来决定刷新间隔。

公开(公告)号：US5841315A

公开(公告)日：1998-11-24

申请号：US686958

申请日：1996-07-26

申请人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Xiaoling Qin ,  Shengmin Lin ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03M1/66 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H03M3/02 ,  H03K5/00 ,  G11C27/02 ,  H03K12/00

CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254 ,  H04B1/7117

摘要： An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

摘要翻译： 本发明的目的是提供一种尺寸小且消耗低功率的匹配滤波电路。 注意扩展码是1位数据串，输入信号被采样并保持为沿着时间序列的模拟信号，分为“1”和“-1”，分类信号通过电容耦合并联 在根据本发明的匹配滤波器电路中。

公开(公告)号：US5835387A

公开(公告)日：1998-11-10

申请号：US791022

申请日：1997-01-27

申请人： Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

发明人： Gouliang Shou ,  Kazunori Motohashi ,  Sunao Takatori ,  Makoto Yamamoto

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X.sub.i corresponding to each element of the first input data string is input to capacitance switching circuits 10.sub.1 to 10.sub.n through input terminals 1.sub.1 to 1.sub.n. m bit of digital control data A.sub.i corresponding to each element of the second input data string are input to each capacitance switching circuit 10.sub.i, and each bit a.sub.j of the control signal A.sub.j is input to the corresponding multiplexer circuit 6.sub.ij. In the multiplexer circuit 6.sub.ij, the capacitances C.sub.ij corresponding to the value of each bit of the control signal a.sub.j are connected to the input terminal 1.sub.i or the reference charge V.sub.STD. The voltages corresponding to the products of inputted analog voltages X.sub.1 and the control signals A.sub.i are outputted from each capacitance switching circuit 10.sub.j. The output voltages of each capacitance switching circuit 10.sub.i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

摘要翻译： 执行乘法，包括由少量硬件高速累积。 对应于第一输入数据串的每个元件的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在复用器电路6ij中，与控制信号aj的每个位的值相对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10j输出与输入的模拟电压X1的乘积对应的电压和控制信号Ai。 每个电容切换电路10i的输出电压被并行地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。