公开(公告)号：US08055978B2

公开(公告)日：2011-11-08

申请号：US11830461

申请日：2007-07-30

Applicant: Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

Inventor： Sun Kwon Kim ,  Byeong Hoon Lee ,  Ki Hong Kim ,  Seung Won Lee

IPC: G11C29/00

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/1068

Abstract: A buffer memory includes a memory cell array, a flag cell array, and a error correction block. The memory cell array has a plurality of word lines. Each of the plurality of word lines are electrically connected to a plurality of memory cells storing data. The flag cell array has a plurality of flag cells. Each of the plurality of flag cells is connected to each of the word lines and stores information that indicates whether error correction of the data has been performed. The error correction block performs error correction on the data output from the memory cell array in response to a command received through a host interface and flag data output from the flag cell array.

Abstract translation: 缓冲存储器包括存储单元阵列，标志单元阵列和纠错块。 存储单元阵列具有多个字线。 多个字线中的每一个电连接到存储数据的多个存储单元。 标志单元阵列具有多个标志单元。 多个标志单元中的每一个连接到每个字线，并且存储指示是否已经执行了数据的纠错的信息。 误差校正块响应于通过主机接口接收的命令和从标志单元阵列输出的标志数据对从存储器单元阵列输出的数据执行纠错。

公开(公告)号：US07590022B2

公开(公告)日：2009-09-15

申请号：US11623575

申请日：2007-01-16

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: G11C17/18

CPC classification number: H01L23/525 ,  G11C16/04 ,  G11C16/0441 ,  G11C16/28 ,  G11C17/165 ,  G11C29/027 ,  G11C29/50 ,  G11C2029/1204 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electric fuse circuit including a first nonvolatile memory cell connected to a first bit line, a second nonvolatile memory cell connected to a second bit line, a latch connected to the first and second bit lines, and a bias current circuit supplying one of the first and second bit lines with variable bias currents through the latch in response to a bias control signal during a test operation.

Abstract translation: 一种电熔丝电路，包括连接到第一位线的第一非易失性存储单元，连接到第二位线的第二非易失性存储单元，连接到第一和第二位线的锁存器，以及提供第一位线之一的偏置电流电路 以及响应于测试操作期间的偏置控制信号，通过锁存器具有可变偏置电流的第二位线。

公开(公告)号：US20090095955A1

公开(公告)日：2009-04-16

申请号：US12249495

申请日：2008-10-10

Applicant: Sun-Kwon Kim ,  Byeong-Hoon Lee ,  Ki-Hong Kim ,  Hyuck-Jun Cho

Inventor： Sun-Kwon Kim ,  Byeong-Hoon Lee ,  Ki-Hong Kim ,  Hyuck-Jun Cho

IPC: H01L23/58

CPC classification number: G06K19/0723

Abstract: A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal.

Abstract translation: 一种包括检测器和安全检查器的半导体集成电路。 该检测器在感测半导体集成电路的工作环境中的异常状态时产生检测信号。 安全检查器产生检查信号以找到检测器的操作条件并接收检测信号。 检测器响应于检查信号激活检测信号。

公开(公告)号：US20080181008A1

公开(公告)日：2008-07-31

申请号：US11693106

申请日：2007-03-29

Applicant: Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Byeong-Hoon Lee ,  Ki-Hong Kim ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/20

Abstract: A flash memory system capable of improving an access performance and an access method thereof. The system includes: a flash memory device including a plurality of storage regions; a contents memory storing setting information corresponding to the plurality of storage regions, respectively; and a processing unit setting operation conditions of the flash memory device by referring to the setting information during an access operation for the flash memory device.

Abstract translation: 一种能够提高访问性能的闪存系统及其访问方法。 该系统包括：闪存器件，包括多个存储区域; 内容存储器，分别存储与所述多个存储区域相对应的设置信息; 以及处理单元，在闪速存储器件的访问操作期间参考设置信息来设置闪速存储器件的操作条件。

公开(公告)号：US20080157730A1

公开(公告)日：2008-07-03

申请号：US11740632

申请日：2007-04-26

Applicant: Young-Taek Kim ,  Byeong-Hoon Lee

Inventor： Young-Taek Kim ,  Byeong-Hoon Lee

IPC: G05F1/10

CPC classification number: H02M3/156 ,  G11C5/145 ,  G11C16/30 ,  H02M2001/0025

Abstract: A high-voltage generation circuit used for a non-volatile memory device reduces the overshoot of a high voltage by controlling a current for sensing the high voltage based on the level of the high voltage or by delaying the operation of an oscillator, which generates a clock signal for generating the high voltage, for a predetermined period of time.

Abstract translation: 用于非易失性存储器件的高电压发生电路通过控制用于基于高电压电平感测高电压的电流或通过延迟振荡器的操作来控制高电压的过冲，从而产生 用于产生高电压的时钟信号预定的时间段。

公开(公告)号：US07300071B2

公开(公告)日：2007-11-27

申请号：US11003434

申请日：2004-12-06

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/11

CPC classification number: B62D1/195

Abstract: A shock absorbing device for steering columns, which has a bracket and a capsule placed around a capsule locking slot of the bracket and fastened along with the bracket to a vehicle body by a locking bolt, is disclosed. The capsule includes an upper plate, a lower plate, and a connector which connects an end of the upper plate to an end of the lower plate. The shock absorbing device further includes a stopper which is provided between the upper plate and the lower plate of the capsule such that the stopper is placed in the capsule locking slot of the bracket. The upper plate of the capsule is bent at an outside edge thereof. The stopper is thinner than the bracket around the capsule locking slot. Furthermore, the upper plate and the lower plate of the capsule are configured such that the upper and lower plates are vertically aligned with each other at outside ends of extensions thereof.

Abstract translation: 公开了一种用于转向柱的减震装置，其具有支架和围绕支架的胶囊锁定槽并且通过锁定螺栓与支架一起固定到车体上的胶囊。 胶囊包括上板，下板和将上板的端部连接到下板的端部的连接器。 该减震装置还包括设置在胶囊的上板和下板之间的止动件，使得止动件被放置在支架的胶囊锁定槽中。 胶囊的上板在其外边缘处弯曲。 塞子比胶囊锁定槽周围的支架更薄。 此外，胶囊的上板和下板被构造成使得上板和下板在其延伸部的外端处彼此垂直对准。

公开(公告)号：US07252019B2

公开(公告)日：2007-08-07

申请号：US10704736

申请日：2003-11-12

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62G1/16

CPC classification number: B62D1/184

Abstract: A tilt device is provided to allow a steering column to be tilted so that a driver can adjust the position of a steering wheel to conform to his/her figure in order to more comfortably drive a vehicle. Further, the tilt device is configured to impart a high supporting strength to the steering column while reliably locking the same.

Abstract translation: 提供倾斜装置以允许转向柱倾斜，使得驾驶员可以调节方向盘的位置以符合他/她的身材，以便更舒适地驾驶车辆。 此外，倾斜装置被构造成在可靠地锁定转向柱的同时赋予转向柱高的支撑强度。

公开(公告)号：US07219927B2

公开(公告)日：2007-05-22

申请号：US11036995

申请日：2005-01-19

Applicant: Byeong-Hoon Lee

Inventor： Byeong-Hoon Lee

IPC: B62D1/00

CPC classification number: B62D1/195

Abstract: A steering column having a variable impact-absorbing structure includes an inner column tube, an outer column tube disposed at an outer circumferential part of the inner column tube, a guide fixed to an outer circumferential surface of the outer column tube, a strap having a deformable part fitted into the guide, a pin inserted through the strap and configured to be slidable into the guide, a solenoid that drives the pin, and a control unit that controls the solenoid. The steering column further includes a sensor that senses a state of a driver and outputs the sensing result to the control unit, wherein the strap comprises a plurality of parallel wires, one end of each wire being opened and the other end of each wire being connected to each other in a closed state, and a suspending end that is bent in a loop shape is formed on the closed end to enable the inner column tube to be suspended thereon.

Abstract translation: 具有可变冲击吸收结构的转向柱包括内柱管，设置在内柱管的外周部的外柱管，固定到外柱管的外周面的引导件，具有 可变形部分装配到引导件中，插入穿过带并被构造成可滑动到引导件中的销，驱动销的螺线管和控制螺线管的控制单元。 转向柱还包括感测驾驶员的状态并将感测结果输出到控制单元的传感器，其中，所述带包括多条平行的线，每条线的一端被打开，并且每条线的另一端被连接 并且在封闭端形成弯曲成环状的悬挂端，使内筒管悬挂在其上。

公开(公告)号：US07183830B2

公开(公告)日：2007-02-27

申请号：US11168659

申请日：2005-06-28

Applicant: Sun-Kwon Kim ,  Byeong Hoon Lee

Inventor： Sun-Kwon Kim ,  Byeong Hoon Lee

IPC: G06F1/04

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit for generating a clock signal includes a voltage conversion unit, a maximum power determination unit, a clock control unit and a clock generator. The voltage conversion unit converts an external power supply voltage into an internal power supply voltage and detects a variance in current consumption of a functional block to generate a detected voltage, wherein the functional block consumes a predetermined current using the internal power supply voltage. The maximum power determination unit determines a maximum current consumption of the functional block and converts the maximum current consumption to a corresponding maximum allowed voltage. The clock control unit generates at least one frequency control signal based on a comparison between the detected voltage and the maximum allowed voltage. The clock generator generates the clock signal whose frequency is adjusted according to the frequency control signal.

Abstract translation: 用于产生时钟信号的集成电路包括电压转换单元，最大功率确定单元，时钟控制单元和时钟发生器。 电压转换单元将外部电源电压转换为内部电源电压，并且检测功能块的电流消耗的变化以产生检测到的电压，其中功能块使用内部电源电压消耗预定电流。 最大功率确定单元确定功能块的最大电流消耗，并将最大电流消耗转换为对应的最大允许电压。 时钟控制单元基于检测到的电压和最大允许电压之间的比较产生至少一个频率控制信号。 时钟发生器产生频率根据频率控制信号进行调整的时钟信号。

公开(公告)号：US07035162B2

公开(公告)日：2006-04-25

申请号：US10873104

申请日：2004-06-21

Applicant: Hwi-taek Chung ,  Byeong-hoon Lee

Inventor： Hwi-taek Chung ,  Byeong-hoon Lee

IPC: G11C8/00

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14

Abstract: A memory device includes a predecoder that receives a row address and responsively generates a plurality of memory block selection signals, a plurality of word line selection signals, a plurality of source line selection signals, and a plurality of sub-block selection signals including respective groups of signals that correspond to respective levels of a hierarchy of sub-blocks in a plurality of memory blocks. The device further includes a global decoder that receives the sub-block selection signals and responsively generates segment activation signals for respective segments of memory blocks that correspond to respective sub-blocks at a lowest level of the hierarchy of sub-blocks. A plurality of word line decoders are coupled to word lines of respective ones of plurality of the memory blocks, with each word line decoder configured to receive the segment activation signals, a memory block selection signal and the word line selection signals and to responsively generate word line signals on the word lines coupled thereto. A plurality of source line decoders are coupled to source lines of respective ones of the plurality of memory blocks, each source line decoder configured to receive the segment activation signals, with a memory block selection signal, and the source line selection signals and to responsively generate source line signals one the source lines coupled thereto.

Abstract translation: 一种存储装置，包括接收行地址并响应地产生多个存储块选择信号的预解码器，多个字线选择信号，多个源极线选择信号和包括各组的多个子块选择信号 的信号，其对应于多个存储块中的子块的层级的各个级别。 该设备还包括全局解码器，其接收子块选择信号，并且响应于生成对应于子块层级的最低级别处的相应子块的存储器块的各个段的段激活信号。 多个字线解码器被耦合到多个存储块中的各个字线的字线，每个字线解码器被配置为接收段激活信号，存储块选择信号和字线选择信号，并响应地产生字 在与其耦合的字线上的线信号。 多个源极线解码器被耦合到多个存储器块中的相应源的源极线，每个源极线解码器被配置为利用存储器块选择信号和源极线选择信号接收段激活信号，并且响应地产生 源极线将与其耦合的源极线信号一个。