公开(公告)号：US20070275530A1

公开(公告)日：2007-11-29

申请号：US11308899

申请日：2006-05-24

申请人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

发明人： Wen-Han Hung ,  Cheng-Tung Huang ,  Da-Ching Chiou ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzermin Shen ,  Tzyy-Ming Cheng

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/26513 ,  H01L29/665 ,  H01L29/6653

摘要： A semiconductor structure and a method of fabricating the same are provided. A substrate having a metal-oxide-semiconductor transistor is provided. The metal-oxide-semiconductor transistor includes a gate, a source/drain extended region, a first spacer, a liner, a source/drain and a metal silicide layer. A portion of the first spacer is removed to form a second spacer by performing an etching process. A contact etching stop layer is formed over the substrate.

摘要翻译： 提供半导体结构及其制造方法。 提供具有金属氧化物半导体晶体管的衬底。 金属氧化物半导体晶体管包括栅极，源极/漏极延伸区域，第一间隔物，衬垫，源极/漏极和金属硅化物层。 通过进行蚀刻处理，去除第一间隔物的一部分以形成第二间隔物。 接触蚀刻停止层形成在衬底上。

公开(公告)号：US20070257321A1

公开(公告)日：2007-11-08

申请号：US11777973

申请日：2007-07-13

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Tzyy-Ming Cheng

IPC分类号： H01L29/76 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.

摘要翻译： 对半导体结构体的制造方法进行说明。 提供了一种衬底，其上具有栅极结构和在栅极结构的侧壁上的隔离物，并且在栅极结构旁边具有S / D延伸区域。 在衬垫旁边的衬底上形成开口，然后在开口的底部形成有基底上的S / D区域。 在S / D区域和栅极结构上形成金属硅化物层，然后在基板上形成应力层。

公开(公告)号：US20070252218A1

公开(公告)日：2007-11-01

申请号：US11776562

申请日：2007-07-12

申请人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

发明人： Kun-Hsien Lee ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Shyh-Fann Ting ,  Li-Shian Jeng ,  Tzyy-Ming Cheng ,  Chia-Wen Lang

IPC分类号： H01L27/092

CPC分类号： H01L21/823412 ,  H01L21/823468 ,  H01L29/7842

摘要： A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress layer and a second stress layer. The first stress layer is disposed on the first-type MOS transistor, or on the first-type MOS transistor and the I/O second-type MOS transistor. The second stress layer is disposed on the core second-type MOS transistor.

摘要翻译： 本文提供了一种半导体器件，其包括具有第一型MOS晶体管，形成在其上的输入/输出（I / O）第二型MOS晶体管和核心第二型MOS晶体管的衬底。 半导体器件还包括第一应力层和第二应力层。 第一应力层设置在第一型MOS晶体管上或第一型MOS晶体管和I / O第二型MOS晶体管上。 第二应力层设置在芯型二次型MOS晶体管上。

公开(公告)号：US20070238241A1

公开(公告)日：2007-10-11

申请号：US11755669

申请日：2007-05-30

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Li-Shian Jeng ,  Kun-Hsien Lee ,  Tzyy-Ming Cheng ,  Jing-Chang Wu ,  Tzermin Shen

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second conductivity type. The first MOS transistor is disposed on the second well, including a gate structure on the second well and a strained layer of the first conductivity type in an opening in the second well beside the gate structure. The difference between the cell parameter of a portion of the strained layer near the bottom of the opening and that of the substrate is less than the difference between the cell parameter of a portion of the strained layer apart from the bottom of the opening and that of the substrate. The second MOS transistor is disposed on the first well.

摘要翻译： 公开了一种半导体结构，包括其中具有第一导电类型的第一阱和第二导电类型的第二阱的衬底，第一导电类型的第一MOS晶体管和第二导电类型的第二MOS晶体管。 第一MOS晶体管设置在第二阱上，包括在第二阱上的栅极结构和位于栅极结构旁边的第二阱中的开口中的第一导电类型的应变层。 开口底部附近的应变层的一部分的单元参数与基板的单元参数之间的差异小于与开口底部之间的应变层的一部分的单元参数之间的差， 底物。 第二MOS晶体管设置在第一阱上。

公开(公告)号：US20070187727A1

公开(公告)日：2007-08-16

申请号：US11307660

申请日：2006-02-16

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L29/80

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US20070111416A1

公开(公告)日：2007-05-17

申请号：US11164177

申请日：2005-11-14

申请人： Cheng-Tung Huang ,  Chia-Wen Liang ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Cheng-Tung Huang ,  Chia-Wen Liang ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L21/8234 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7843 ,  H01L29/6653 ,  Y10S438/938

摘要： A method of fabricating strained-silicon transistors includes providing a semiconductor substrate, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region; performing a first rapid thermal annealing (RTA) process; removing the spacer and forming a high tensile stress film over the surface of the gate and the source/drain region; and performing a second rapid thermal annealing process.

摘要翻译： 制造应变硅晶体管的方法包括：提供半导体衬底，其中半导体衬底包括栅极，至少间隔物和源极/漏极区域; 执行第一快速热退火（RTA）工艺; 去除间隔物并在栅极和源极/漏极区域的表面上形成高拉伸应力膜; 并进行第二快速热退火处理。

公开(公告)号：US20060228847A1

公开(公告)日：2006-10-12

申请号：US10907342

申请日：2005-03-30

申请人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Yi-Cheng Liu ,  Wen-Chi Chen ,  Tzu-Yun Chang ,  Bang-Chiang Lan ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814

摘要： First, a substrate having a plurality of NMOS transistor regions and PMOS transistor regions is provided. The substrate further includes a plurality of gate structures respectively positioned in the NMOS transistor regions and the PMOS transistor regions. A high-tensile thin film is then formed on the substrate and the plurality of gate structures. Subsequently, an annealing process is performed, and the high-tensile thin film is removed after the annealing process.

摘要翻译： 首先，提供具有多个NMOS晶体管区域和PMOS晶体管区域的衬底。 衬底还包括分别位于NMOS晶体管区域和PMOS晶体管区域中的多个栅极结构。 然后在基板和多个栅极结构上形成高拉伸薄膜。 随后，进行退火处理，并且在退火处理之后去除高拉伸薄膜。

公开(公告)号：US20060228843A1

公开(公告)日：2006-10-12

申请号：US10907677

申请日：2005-04-12

申请人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

发明人： Alex Liu ,  Cheng-Tung Huang ,  Wei-Tsun Shiau ,  Kuan-Yang Liao

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845 ,  Y10S438/938

摘要： A method of fabricating semiconductor devices is provided. A plurality of gate structures is formed over a substrate. A source region and a drain region are formed in the substrate and adjacent to sidewalls of each gate structure. A self-aligned salicide block (SAB) layer is formed over the substrate to cover the gate structures and the exposed surface of the substrate. An anneal process is performed. The SAB layer creates a tension stress during the anneal process so that the substrate under the gate structures is subjected to the tension stress. A portion of the SAB layer is removed to expose a portion of the gate structures and a portion of the surface of the substrate. A salicide process is performed.

摘要翻译： 提供一种制造半导体器件的方法。 在衬底上形成多个栅极结构。 源极区域和漏极区域形成在衬底中并且邻近每个栅极结构的侧壁。 在衬底上形成自对准的自对准硅化物块（SAB）层以覆盖栅极结构和衬底的暴露表面。 进行退火处理。 SAB层在退火过程中产生拉伸应力，使得栅极结构下的基板受到张力应力。 去除SAB层的一部分以暴露栅极结构的一部分和衬底表面的一部分。 执行自杀化合物处理。

公开(公告)号：US20050280068A1

公开(公告)日：2005-12-22

申请号：US10908577

申请日：2005-05-18

申请人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/732

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

摘要翻译： 闪存单元包括第一导电类型衬底，堆叠栅极结构，第一导电类型源极/漏极区域，金属硅化物层，层间电介质层和接触插塞。 第一导电型衬底具有已经形成在其上的第二导电型浅阱。 金属硅化物层设置在第一导电类型漏极区域内。 接触插塞设置在层间电介质层内并与第一导电类型漏极区域中的金属硅化物层电连接，以减小接触插塞，第一导电类型漏极区域和第二导电类型浅阱之间的电阻，并增加 闪存的读出速度。

公开(公告)号：US06955929B2

公开(公告)日：2005-10-18

申请号：US10709236

申请日：2004-04-23

申请人： Cheng-Tung Huang ,  Sheng-Hao Lin ,  Nien-Chung Li ,  Yi-Cheng Sheng

发明人： Cheng-Tung Huang ,  Sheng-Hao Lin ,  Nien-Chung Li ,  Yi-Cheng Sheng

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34

摘要： A predetermined voltage is applied respectively on a first gate of a first metal-oxide semiconductor (MOS) transistor with a known channel length and a second gate of a second MOS transistor with an unknown channel length. A first inverse gate leakage current of the first MOS transistor and a second inverse gate leakage current of the second MOS transistor are then measured. By using the first and second inverse gate leakage currents, the channel widths of the first and the second gates, the channel length of the first gate and an equation, the channel length of the second gate is obtained.

摘要翻译： 分别在具有未知通道长度的已知沟道长度的第一金属氧化物半导体（MOS）晶体管的第一栅极和第二MOS晶体管的第二栅极上施加预定电压。 然后测量第一MOS晶体管的第一反向栅极漏电流和第二MOS晶体管的第二反向栅极漏电流。 通过使用第一和第二反向栅极泄漏电流，获得第一和第二栅极的沟道宽度，第一栅极的沟道长度和等式，获得第二栅极的沟道长度。