公开(公告)号：US20060216893A1

公开(公告)日：2006-09-28

申请号：US11308806

申请日：2006-05-09

申请人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A manufacturing method of a flash memory cell is provided. The flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

摘要翻译： 提供了闪存单元的制造方法。 闪存单元包括第一导电类型衬底，堆叠栅极结构，第一导电类型源极/漏极区域，金属硅化物层，层间电介质层和接触插塞。 第一导电型衬底具有已经形成在其上的第二导电型浅阱。 金属硅化物层设置在第一导电类型漏极区域内。 接触插塞设置在层间电介质层内并与第一导电类型漏极区域中的金属硅化物层电连接，以减小接触插塞，第一导电类型漏极区域和第二导电类型浅阱之间的电阻，并增加 闪存的读出速度。

公开(公告)号：US20050280068A1

公开(公告)日：2005-12-22

申请号：US10908577

申请日：2005-05-18

申请人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Chao-Wei Kuo ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/732

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell includes a first conductive type substrate, a stacked gate structure, a first conductive type source/drain region, a metal silicide layer, an inter-layer dielectric layer and a contact plug. The first conductive type substrate has a second conductive type shallow well already formed thereon. The metal silicide layer is disposed within the first conductive type drain region. The contact plug is disposed within the inter-layer dielectric layer and electrically connected with the metal silicide layer in the first conductive type drain region to reduce resistance between the contact plug, the first conductive type drain region and the second conductive type shallow well and increase read-out speed of the flash memory.

摘要翻译： 闪存单元包括第一导电类型衬底，堆叠栅极结构，第一导电类型源极/漏极区域，金属硅化物层，层间电介质层和接触插塞。 第一导电型衬底具有已经形成在其上的第二导电型浅阱。 金属硅化物层设置在第一导电类型漏极区域内。 接触插塞设置在层间电介质层内并与第一导电类型漏极区域中的金属硅化物层电连接，以减小接触插塞，第一导电类型漏极区域和第二导电类型浅阱之间的电阻，并增加 闪存的读出速度。

公开(公告)号：US20060008981A1

公开(公告)日：2006-01-12

申请号：US10905189

申请日：2004-12-21

申请人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

摘要翻译： 一种闪存单元，包括第一导电类型衬底，第二导电类型阱，图案化膜层，第二导电类型掺杂区域，隧道电介质层，多个浮置栅极，栅极间介电层和多个 提供控制门。 浮置栅极形成在图案化膜层外部的第一导电类型基板上。 浮动栅极的厚度大于图案化的膜层。 因此，浮动栅极和控制栅极之间的重叠区域以及闪存单元的耦合比例增加。

公开(公告)号：US06984559B2

公开(公告)日：2006-01-10

申请号：US10709640

申请日：2004-05-19

申请人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are formed over the active region. A portion of each device isolation structure is removed to form a plurality of trenches. A dielectric layer is formed over the substrate and a sacrificial layer is filled the trenches. A portion of the dielectric layer is removed using the sacrificial layer as a self-aligned mask. The patterned mask layer is removed and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer and a control gate are formed over the substrate. A source region and a drain region are formed in the substrate on each side of the control gate.

摘要翻译： 提供一种制造闪速存储器的方法。 提供了具有用于限定有源区域的多个器件隔离结构的衬底。 隧道电介质层和图案化掩模层形成在有源区上。 每个器件隔离结构的一部分被去除以形成多个沟槽。 介电层形成在衬底上并且牺牲层填充沟槽。 使用牺牲层作为自对准掩模去除介电层的一部分。 去除图案化的掩模层，并且在衬底上形成暴露牺牲层的顶部的导电层。 在去除牺牲层之后，在衬底上形成栅极间介电层和控制栅极。 源极区域和漏极区域形成在控制栅极的每一侧上的衬底中。

公开(公告)号：US20050176200A1

公开(公告)日：2005-08-11

申请号：US10709640

申请日：2004-05-19

申请人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are formed over the active region. A portion of each device isolation structure is removed to form a plurality of trenches. A dielectric layer is formed over the substrate and a sacrificial layer is filled the trenches. A portion of the dielectric layer is removed using the sacrificial layer as a self-aligned mask. The patterned mask layer is removed and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer and a control gate are formed over the substrate. A source region and a drain region are formed in the substrate on each side of the control gate.

摘要翻译： 提供一种制造闪速存储器的方法。 提供了具有用于限定有源区域的多个器件隔离结构的衬底。 隧道电介质层和图案化掩模层形成在有源区上。 每个器件隔离结构的一部分被去除以形成多个沟槽。 介电层形成在衬底上并且牺牲层填充沟槽。 使用牺牲层作为自对准掩模去除介电层的一部分。 去除图案化的掩模层，并且在衬底上形成暴露牺牲层的顶部的导电层。 在去除牺牲层之后，在衬底上形成栅极间介电层和控制栅极。 源极区域和漏极区域形成在控制栅极的每一侧上的衬底中。

公开(公告)号：US06893918B1

公开(公告)日：2005-05-17

申请号：US10709639

申请日：2004-05-19

申请人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

发明人： Leo Wang ,  Chien-Chih Du ,  Saysamone Pittikoun

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory is provided. A substrate having several device isolation structures for defining an active region is provided. A tunneling dielectric layer and a patterned mask layer are sequentially formed over the active region of the substrate. A sacrificial layer is formed on the substrates. Thereafter, the sacrificial layer is patterned to retain a part of sacrificial layer on the device isolation structures. The patterned mask layer is removed, and a conductive layer that exposed the top section of the sacrificial layers is formed over the substrate. After removing the sacrificial layer, an inter-gate dielectric layer is formed over the substrate. A control gate is formed over the inter-gate dielectric layer. Finally, a source region and a drain region are formed in the substrate on each side of the control gate.

摘要翻译： 提供一种制造闪速存储器的方法。 提供了具有用于限定有源区域的多个器件隔离结构的衬底。 在衬底的有源区上依次形成隧穿电介质层和图案化掩模层。 在基板上形成牺牲层。 此后，牺牲层被图案化以将牺牲层的一部分保留在器件隔离结构上。 去除图案化的掩模层，并且在衬底上形成暴露牺牲层的顶部的导电层。 在去除牺牲层之后，在衬底上形成栅极间电介质层。 在栅极间电介质层上形成控制栅极。 最后，在控制栅极的每一侧的基板上形成源极区域和漏极区域。

公开(公告)号：US07445999B2

公开(公告)日：2008-11-04

申请号：US11461778

申请日：2006-08-02

申请人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

摘要翻译： 一种闪存单元，包括第一导电类型衬底，第二导电类型阱，图案化膜层，第二导电类型掺杂区域，隧道电介质层，多个浮置栅极，栅极间介电层和多个 提供控制门。 浮置栅极形成在图案化膜层外部的第一导电类型基板上。 浮动栅极的厚度大于图案化的膜层。 因此，浮动栅极和控制栅极之间的重叠区域以及闪存单元的耦合比例增加。

公开(公告)号：US07109082B2

公开(公告)日：2006-09-19

申请号：US10905189

申请日：2004-12-21

申请人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

摘要翻译： 一种闪存单元，包括第一导电类型衬底，第二导电类型阱，图案化膜层，第二导电类型掺杂区域，隧道电介质层，多个浮置栅极，栅极间介电层和多个 提供控制门。 浮置栅极形成在图案化膜层外部的第一导电类型基板上。 浮动栅极的厚度大于图案化的膜层。 因此，浮动栅极和控制栅极之间的重叠区域以及闪存单元的耦合比例增加。

公开(公告)号：US20060263978A1

公开(公告)日：2006-11-23

申请号：US11461778

申请日：2006-08-02

申请人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

发明人： Leo Wang ,  Cheng-Tung Huang ,  Saysamone Pittikoun

IPC分类号： H01L21/8242

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory cell including a first conductive type substrate, a second conductive type well, a patterned film layer, a second conductive type doped region, a tunneling dielectric layer, a plurality of floating gates, an inter-gate dielectric layer and a plurality of control gates is provided. The floating gates are formed on the first conductive type substrate outside the patterned film layer. The floating gates have a thickness greater than the patterned film layer. Thus, the overlapping area between the floating gates and the control gates and hence the coupling ratio of the flash memory cell is increased.

摘要翻译： 一种闪存单元，包括第一导电类型衬底，第二导电类型阱，图案化膜层，第二导电类型掺杂区域，隧道电介质层，多个浮置栅极，栅极间介电层和多个 提供控制门。 浮置栅极形成在图案化膜层外部的第一导电类型基板上。 浮动栅极的厚度大于图案化的膜层。 因此，浮动栅极和控制栅极之间的重叠区域以及闪存单元的耦合比例增加。

公开(公告)号：US20050093055A1

公开(公告)日：2005-05-05

申请号：US10709505

申请日：2004-05-11

申请人： Leo Wang ,  Chien-Chih Du ,  Da Sung ,  Chih-Wei Hung ,  Vincent Huang

发明人： Leo Wang ,  Chien-Chih Du ,  Da Sung ,  Chih-Wei Hung ,  Vincent Huang

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  G11C11/34

CPC分类号： H01L21/28202 ,  G11C16/0416 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/511 ,  H01L29/66825 ,  H01L29/7883

摘要： A substrate having a P type shallow doped region is provided, and at least a stacked gate structure having a tunneling oxide, a floating gate, an ONO layer, and a control gate from bottom to top are respectively formed thereon. Then, a P type deep doped region is formed in the substrate alongside the stacked gate structure. Following that, an oxidization process is performed to oxidize the floating gate and the control gate such that an insulating barrier layer is formed. Finally, a drain and a source are formed in the substrate.

摘要翻译： 提供了具有P型浅掺杂区域的衬底，并且至少在其上分别形成有从底部到顶部具有隧道氧化物，浮动栅极，ONO层和控制栅极的堆叠栅极结构。 然后，在堆叠的栅极结构旁边的衬底中形成P型深掺杂区域。 之后，进行氧化处理以使浮栅和控制栅极氧化，从而形成绝缘阻挡层。 最后，在衬底中形成漏极和源极。