公开(公告)号：US12033033B2

公开(公告)日：2024-07-09

申请号：US17607278

申请日：2020-06-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Kelly T. R. Boothby

IPC: G06N10/40 ,  H10N60/12 ,  H10N60/80

CPC classification number: G06N10/40 ,  H10N60/12 ,  H10N60/805

Abstract: A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.

公开(公告)号：US20240185104A1

公开(公告)日：2024-06-06

申请号：US18385226

申请日：2023-10-30

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H. AMIN ,  Trevor Michael LANTING ,  Colin ENDERUD

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.

公开(公告)号：US20240168720A1

公开(公告)日：2024-05-23

申请号：US18113735

申请日：2023-02-24

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H. Amin

IPC: G06F7/58 ,  G06N10/40 ,  H04L9/08

CPC classification number: G06F7/582 ,  G06N10/40 ,  H04L9/0852

Abstract: Systems and methods for random number generation are discussed. A first processor is in communication with a quantum processor, the quantum processor having an array of superconducting qubits. The first processor instructs the quantum processor to selectively communicatively couple the superconducting qubits to embed a quantum system having a highly entangled nontrivial ground state. The highly entangled nontrivial ground state comprising a uniform distribution of classical ground states. One or more distortions are introduced to the uniform distribution by one or more random variations based on an input value. The quantum processor evolves over the embedded quantum system. A set of one or more random numbers is received from the quantum processor.

公开(公告)号：US20240151782A1

公开(公告)日：2024-05-09

申请号：US18517174

申请日：2023-11-22

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  Emile M. Hoskinson ,  Mark H. Volkmann ,  Andrew J. Berley ,  George E.G. Sterling ,  Jed D. Whittaker

IPC: G01R33/035 ,  G06N10/00 ,  H10N60/12

CPC classification number: G01R33/0354 ,  G06N10/00 ,  H10N60/12

Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.

公开(公告)号：US20240144068A1

公开(公告)日：2024-05-02

申请号：US18379799

申请日：2023-10-13

Applicant: D-WAVE SYSTEMS INC.

Inventor： Anil Mahmud

IPC: G06N10/60

CPC classification number: G06N10/60

Abstract: Systems and methods for operation of a computing system to direct a search space for an optimization problem are described. One or more processors initialize an optimization algorithm, and iteratively until a termination criteria is met: receive a sample solution from the optimization algorithm, evaluate quality and feasibility of the sample solution, and where the sample solution is feasible and has the best quality so far, freeze one or more penalty parameters for a set number of iterations. Where the sample solution is not feasible or does not have the best quality so far, the one or more penalty parameters are updated based on a finite state machine, the updated one or more penalty parameters are returned to the optimization algorithm, the optimization algorithm is incremented, the termination criteria is evaluated, and when the termination criteria is met, one or more sample solutions are returned.

公开(公告)号：US20240138268A1

公开(公告)日：2024-04-25

申请号：US18277688

申请日：2022-02-17

Applicant: D-WAVE SYSTEMS INC.

Inventor： Colin C. Enderud ,  Mohammad H. Amin ,  Loren J. Swenson

IPC: H10N60/01 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18 ,  H10N60/12 ,  H10N60/80 ,  H10N69/00

CPC classification number: H10N60/0912 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53285 ,  H01L25/18 ,  H10N60/12 ,  H10N60/805 ,  H10N69/00

Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material. A superconducting integrated circuit has a first stack with a first superconducting wiring layer formed from a first high kinetic inductance material and a second superconducting wiring layer communicatively coupled to the first superconducting wiring layer to form a first control circuit, a second stack comprising a third superconducting wiring layer formed from a second high kinetic inductance material and a fourth superconducting wiring layer communicatively coupled the third superconducting wiring layer to form a second control circuit. The superconducting integrated circuit also has a third stack with a controllable device, and at least one of the first control circuit and the second control circuit is communicatively coupled to the controllable device.

公开(公告)号：US11930721B2

公开(公告)日：2024-03-12

申请号：US16870537

申请日：2020-05-08

Applicant: D-WAVE SYSTEMS INC.

Inventor： Eric Ladizinsky ,  Jeremy P. Hilton ,  Byong Hyop Oh ,  Paul I. Bunyk

IPC: H10N60/01 ,  B82Y10/00 ,  H01L21/285 ,  H01L21/768 ,  H10N60/10 ,  H10N60/12 ,  H10N60/80 ,  H10N60/85 ,  H10N69/00 ,  G06N10/00

CPC classification number: H10N60/0912 ,  B82Y10/00 ,  H01L21/2855 ,  H01L21/76877 ,  H01L21/76891 ,  H10N60/01 ,  H10N60/0156 ,  H10N60/10 ,  H10N60/12 ,  H10N60/805 ,  H10N60/855 ,  H10N69/00 ,  G06N10/00

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

公开(公告)号：US20240028938A1

公开(公告)日：2024-01-25

申请号：US17742587

申请日：2022-05-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Andrew J. Berkley ,  Ilya V. Perminov

IPC: G06N10/20 ,  G06N10/40

CPC classification number: G06N10/20 ,  G06N10/40

Abstract: Methods and systems for calibrating quantum processors are discussed. A model of a portion of the processor to be calibrated has one or more determinable parameters and an uncertainty for the determinable parameter(s). A measurement procedure is iteratively performed by selecting a subset of possible measurements and generating predicted measurement outcomes and predicted uncertainties for the determinable parameter for each measurement in the subset of possible measurements. Based on the predicted reduction in uncertainty for the determinable parameter, one or more measurements is selected. Instructions are transmitted to the quantum processor to perform the selected measurements, and the results are returned to update the model of the portion of the processor to be calibrated. Once a termination criteria is met, a calibrated value is generated for the determinable parameter. Compensating signals can be applied to devices of the quantum processor to calibrate the devices.

公开(公告)号：US11879950B2

公开(公告)日：2024-01-23

申请号：US17054631

申请日：2019-05-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： Loren J. Swenson ,  Emile M. Hoskinson ,  Mark H. Volkmann ,  Andrew J. Berkley ,  George E. G. Sterling ,  Jed D. Whittaker

IPC: G01R33/54 ,  G01R33/035 ,  G06N10/00 ,  H10N60/12

CPC classification number: G01R33/0354 ,  G06N10/00 ,  H10N60/12

Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.

公开(公告)号：US20230400510A1

公开(公告)日：2023-12-14

申请号：US17970853

申请日：2022-10-21

Applicant: D-WAVE SYSTEMS INC.

Inventor： Jed D. Whittaker ,  Richard Harris ,  Rahul Deshpande

IPC: G01R31/317

CPC classification number: G01R31/31702 ,  G01R31/31709

Abstract: Systems and methods for measuring noise in discrete regions of multi-layer superconducting fabrication stacks are described. Methods for measuring noise in spatial regions of a superconducting fabrication stacks may include the use of resonators, each having a different geometry. As many resonators as spatial regions are fabricated. Data collected from the resonators may be used to calculate fill fractions and spin densities for different spatial regions of the superconducting fabrication stack. The data may be collected via on-chip electron-spin resonance. The superconducting fabrications may be part of a fabrication stack for a superconducting processor, for example a quantum processor, and the spatial region studied may be proximate to qubit wiring layers.