公开(公告)号：US07714407B2

公开(公告)日：2010-05-11

申请号：US11847201

申请日：2007-08-29

Applicant: Florin Udrea ,  Cerdin Lee

Inventor： Florin Udrea ,  Cerdin Lee

IPC: H01L29/00 ,  H01L21/8238

CPC classification number: H01L29/861 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

Abstract translation: 高电压/功率半导体器件具有具有高电压终端和低电压终端的半导体层。 漂移区域在高压端子和低压端子之间延伸。 在漂移区域的上方设置电介质层。 电导体延伸穿过漂移区域上方的电介质层的至少一部分，电导体连接或连接到高电压终端。 漂移区域具有位于电导体下方的多个沟槽。 沟槽横跨横穿半导体层的高压端子和低电压端子之间的方向横向延伸穿过漂移区域的至少一部分，每个沟槽包含电介质材料。 沟槽在电导体存在的情况下改善了器件中电场的分布。

公开(公告)号：US20090283796A1

公开(公告)日：2009-11-19

申请号：US12186966

申请日：2008-08-06

Applicant: Florin Udrea ,  Chih-Wei Hsu

Inventor： Florin Udrea ,  Chih-Wei Hsu

IPC: H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical drift region of a first conductivity type and having vertical first and second ends. In one example, a region of the second conductivity type is provided at the second end of the vertical drift region connected directly to the vertical high voltage terminal. In another example, a vertical buffer region of the first conductivity type is provided at the vertical second end of the vertical drift region and a vertical region of a second conductivity type is provided on the other side of the vertical buffer region and connected to the vertical high voltage terminal. A plurality of electrically floating lateral island regions are provided within the vertical drift region at or towards the vertical second end of the vertical drift region, the plurality of electrically floating lateral island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 公开了一种具有低电压端子和高电压端子的双极型高压/功率半导体器件。 双极性高压/功率半导体是垂直绝缘栅双极晶体管，其具有由p +阳极层中的高掺杂n +岛形成的注入效率调节。 该器件具有第一导电类型的垂直漂移区，并具有垂直的第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到垂直高压端子的垂直漂移区域的第二端。 在另一示例中，第一导电类型的垂直缓冲区域设置在垂直漂移区域的垂直第二端，并且第二导电类型的垂直区域设置在垂直缓冲区域的另一侧并连接到垂直方向 高压端子。 多个电浮动横向岛区域设置在垂直漂移区域内或垂直于垂直漂移区域的垂直第二端处，多个电浮动横向岛区域是第一导电类型并且比漂移更高的掺杂 地区。

公开(公告)号：US07531875B2

公开(公告)日：2009-05-12

申请号：US10556927

申请日：2003-05-13

Applicant: Florin Udrea ,  David Garner

Inventor： Florin Udrea ,  David Garner

IPC: H01L29/94

CPC classification number: H01L29/7824 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/8086 ,  H01L29/861

Abstract: This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

Abstract translation: 本发明通常涉及绝缘体上半导体器件，特别是对于高电压应用。 描述了一种绝缘体侧向半导体器件，包括：半导体衬底; 在所述半导体衬底上的绝缘层; 和在所述绝缘体上的横向半导体器件; 所述横向半导体器件具有：第一导电类型的第一区域; 与所述第一区域横向间隔开的第二导电类型的第二区域; 以及在所述第一区域和所述第二区域之间沿横向方向延伸的漂移区域; 并且其中所述漂移区包括至少一个第一区和邻近所述第一区的至少一个第二区，具有所述第二导电类型的所述第一区，所述第二区是绝缘区，所述第一区逐渐缩窄 朝向第一个地区。

公开(公告)号：US20090057831A1

公开(公告)日：2009-03-05

申请号：US11847201

申请日：2007-08-29

Applicant: Florin Udrea ,  Cerdin Lee

Inventor： Florin Udrea ,  Cerdin Lee

IPC: H01L29/66 ,  H01L21/76

CPC classification number: H01L29/861 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7394 ,  H01L29/7824 ,  H01L29/8611

Abstract: A high voltage/power semiconductor device has a semiconductor layer having a high voltage terminal end and a low voltage terminal end. A drift region extends between the high and low voltage terminal ends. A dielectric layer is provided above the drift region. An electrical conductor extends across at least a part of the dielectric layer above the drift region, the electrical conductor being connected or connectable to the high voltage terminal end. The drift region has plural trenches positioned below the electrical conductor. The trenches extend laterally across at least a part of the drift region in the direction transverse the direction between the high and low voltage terminal ends of the semiconductor layer, each trench containing a dielectric material. The trenches improve the distribution of electric field in the device in the presence of the electrical conductor.

Abstract translation: 高电压/功率半导体器件具有具有高电压终端和低电压终端的半导体层。 漂移区域在高压端子和低压端子之间延伸。 在漂移区域的上方设置电介质层。 电导体延伸穿过漂移区域上方的电介质层的至少一部分，电导体连接或连接到高电压终端。 漂移区域具有位于电导体下方的多个沟槽。 沟槽横跨横穿半导体层的高压端子和低电压端子之间的方向横向延伸穿过漂移区域的至少一部分，每个沟槽包含电介质材料。 沟槽在电导体存在的情况下改善了器件中电场的分布。

公开(公告)号：US07381606B2

公开(公告)日：2008-06-03

申请号：US11873966

申请日：2007-10-17

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20080054439A1

公开(公告)日：2008-03-06

申请号：US11511516

申请日：2006-08-29

Applicant: Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

Inventor： Rajesh Kumar Malhan ,  C. Mark Johnson ,  Cyril Buttay ,  Jeremy Rashid ,  Florin Udrea

IPC: H01L23/48

CPC classification number: H01L23/49844 ,  H01L23/5385 ,  H01L24/31 ,  H01L24/83 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/33 ,  H01L2224/81894 ,  H01L2224/83801 ,  H01L2224/83894 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.

Abstract translation: 电力电子封装包括：第一和第二高导热绝缘非平面基板; 以及基板之间的多个半导体芯片和电子部件。 每个衬底包括多个电绝缘体层和连接到电子部件的图案化电导体层，并且还包括多个凸起区域或柱体，这些凸起区域或柱体被结合在一起，使得衬底机械地和电连接。 调整凸起区域或柱的数量，布置和形状以在基板之间具有机械分离。 电导体层彼此分离和隔离，使得在至少一个基板上设置多个电路。

公开(公告)号：US20070120187A1

公开(公告)日：2007-05-31

申请号：US10556927

申请日：2003-05-13

Applicant: Florin Udrea ,  David Garner

Inventor： Florin Udrea ,  David Garner

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/7824 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/7394 ,  H01L29/8086 ,  H01L29/861

Abstract: This invention is generally concerned with semiconductor-on-insulator devices, particularly for high voltage applications. A lateral semiconductor-on-insulator device is described, comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; and a lateral semiconductor device on said insulator; said lateral semiconductor device having: a first region of a first conductivity type; a second region of a second conductivity type laterally spaced apart from said first region; and a drift region extending in a lateral direction between said first region and said second region; and wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered to narrow towards said first region.

Abstract translation: 本发明通常涉及绝缘体上半导体器件，特别是对于高电压应用。 描述了一种绝缘体侧向半导体器件，包括：半导体衬底; 在所述半导体衬底上的绝缘层; 和在所述绝缘体上的横向半导体器件; 所述横向半导体器件具有：第一导电类型的第一区域; 与所述第一区域横向间隔开的第二导电类型的第二区域; 以及在所述第一区域和所述第二区域之间沿横向方向延伸的漂移区域; 并且其中所述漂移区包括至少一个第一区和邻近所述第一区的至少一个第二区，具有所述第二导电类型的所述第一区，所述第二区是绝缘区，所述第一区逐渐缩窄 朝向第一个地区。

公开(公告)号：US20070102708A1

公开(公告)日：2007-05-10

申请号：US11594896

申请日：2006-11-09

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L31/0312 ,  H01L29/76

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract translation: 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。

公开(公告)号：US07154130B2

公开(公告)日：2006-12-26

申请号：US10776338

申请日：2004-02-12

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L29/74 ,  H01L31/111

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

公开(公告)号：US20060284217A1

公开(公告)日：2006-12-21

申请号：US11501777

申请日：2006-08-10

Applicant: Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/80

CPC classification number: H01L29/8083 ,  H01L29/1608

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract translation: 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。