公开(公告)号：US08970016B2

公开(公告)日：2015-03-03

申请号：US13486614

申请日：2012-06-01

Applicant: Marina Antoniou ,  Florin Udrea ,  Elizabeth Kho Ching Tee ,  Steven John Pilkington ,  Deb Kumar Pal ,  Alexander Dietrich Hölke

Inventor： Marina Antoniou ,  Florin Udrea ,  Elizabeth Kho Ching Tee ,  Steven John Pilkington ,  Deb Kumar Pal ,  Alexander Dietrich Hölke

IPC: H01L29/02

CPC classification number: H01L29/402 ,  H01L21/761 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/7823 ,  H01L29/861

Abstract: A semiconductor device including a p or p+ doped portion and an n or n+ doped portion separated from the p or p+ doped portion by a semiconductor drift portion. The device further includes at least one termination portion provided adjacent to the drift portion. The at least one termination portion comprises a Super Junction structure.

Abstract translation: 一种包括p或p +掺杂部分和通过半导体漂移部分从p或p +掺杂部分分离的n或n +掺杂部分的半导体器件。 该装置还包括邻近漂移部分设置的至少一个终端部分。 所述至少一个终端部分包括超结结构。

公开(公告)号：US08410560B2

公开(公告)日：2013-04-02

申请号：US12691104

申请日：2010-01-21

Applicant: Syed Zeeshan Ali ,  Florin Udrea ,  Julian William Gardner

Inventor： Syed Zeeshan Ali ,  Florin Udrea ,  Julian William Gardner

IPC: H01L27/14 ,  H01L21/00

CPC classification number: H05B3/267 ,  Y10T29/49083

Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature.

Abstract translation: 提供微电子装置的形式包括传感器和微电热板内的一个或多个电阻加热器，其布置成加热传感器。 此外，提供了一种控制器，用于向至少一个加热器施加双向驱动电流以减少电迁移。 控制器还用于以基本恒定的温度驱动加热器。

公开(公告)号：US07994569B2

公开(公告)日：2011-08-09

申请号：US12186966

申请日：2008-08-06

Applicant: Florin Udrea ,  Chih-Wei Hsu

Inventor： Florin Udrea ,  Chih-Wei Hsu

IPC: H01L29/76

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: A bipolar high voltage/power semiconductor device having a low voltage terminal and a high voltage terminal is disclosed. The bipolar high voltage/power semiconductor is a vertical insulated gate bipolar transistor with injection efficiency adjustment formed by highly doped n+ islands in a p+ anode layer. The device has a vertical drift region of a first conductivity type and having vertical first and second ends. In one example, a region of the second conductivity type is provided at the second end of the vertical drift region connected directly to the vertical high voltage terminal. In another example, a vertical buffer region of the first conductivity type is provided at the vertical second end of the vertical drift region and a vertical region of a second conductivity type is provided on the other side of the vertical buffer region and connected to the vertical high voltage terminal. A plurality of electrically floating lateral island regions are provided within the vertical drift region at or towards the vertical second end of the vertical drift region, the plurality of electrically floating lateral island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 公开了一种具有低电压端子和高电压端子的双极型高压/功率半导体器件。 双极性高压/功率半导体是垂直绝缘栅双极晶体管，其具有由p +阳极层中的高掺杂n +岛形成的注入效率调节。 该器件具有第一导电类型的垂直漂移区，并具有垂直的第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到垂直高压端子的垂直漂移区域的第二端。 在另一示例中，第一导电类型的垂直缓冲区域设置在垂直漂移区域的垂直第二端，并且第二导电类型的垂直区域设置在垂直缓冲区域的另一侧并连接到垂直方向 高压端子。 多个电浮动横向岛区域设置在垂直漂移区域内或垂直于垂直漂移区域的垂直第二端处，多个电浮动横向岛区域是第一导电类型并且比漂移更高的掺杂 地区。

公开(公告)号：US07691694B2

公开(公告)日：2010-04-06

申请号：US11785276

申请日：2007-04-17

Applicant: Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L21/337

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/8083 ,  Y10S438/931

Abstract: A silicon carbide semiconductor device includes a substrate and a junction field effect transistor. The transistor includes: a first semiconductor layer disposed on the substrate; a first gate layer disposed on a surface of the first semiconductor layer; a first channel layer adjacent to the first gate layer on the substrate; a first source layer connecting to the first channel layer electrically; a second gate layer adjacent to the first channel layer to sandwich the first channel layer; a second channel layer adjacent to the second gate layer to sandwich the second gate layer; a third gate layer adjacent to the second channel layer to sandwich the second channel layer; and a second source layer connecting to the second channel layer electrically.

Abstract translation: 碳化硅半导体器件包括衬底和结场效应晶体管。 晶体管包括：设置在基板上的第一半导体层; 设置在所述第一半导体层的表面上的第一栅极层; 与所述基板上的所述第一栅极层相邻的第一沟道层; 电连接到第一沟道层的第一源极层; 与所述第一沟道层相邻以夹住所述第一沟道层的第二栅极层; 与所述第二栅极层相邻以夹住所述第二栅极层的第二沟道层; 与所述第二沟道层相邻以夹住所述第二沟道层的第三栅极层; 以及电连接到第二沟道层的第二源极层。

公开(公告)号：US07605446B2

公开(公告)日：2009-10-20

申请号：US11486377

申请日：2006-07-14

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A. J. Amaratunga

IPC: H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/7393 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract translation: 双极高压/功率半导体器件具有分别具有与其不同导电类型的端部区域相邻的漂移区域。 提供高低压端子。 还提供了第一绝缘栅极端子和第二绝缘栅极端子。 一个或多个驱动电路为第一和第二绝缘栅极端子提供适当的电压，以允许在与第一方向相反的第一方向或第二方向上的电流传导。

公开(公告)号：US07589379B2

公开(公告)日：2009-09-15

申请号：US10936721

申请日：2004-09-09

Applicant: Gehan Anil Joseph Amaratunga ,  Florin Udrea

Inventor： Gehan Anil Joseph Amaratunga ,  Florin Udrea

IPC: H01L29/72

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication.A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulating layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

Abstract translation: 本发明一般涉及诸如功率MOS晶体管，双极晶体管（IGBT）的绝缘栅极，高压二极管等功率半导体及其制造方法。 功率半导体，所述半导体包括：功率器件，所述功率器件具有第一和第二电接触区域和在其间延伸的漂移区域; 以及安装所述装置的半导体衬底; 并且其中所述功率半导体在所述半导体衬底和所述功率器件之间包括电绝缘层，所述电绝缘层具有至少5μm的厚度。

公开(公告)号：US20090008674A1

公开(公告)日：2009-01-08

申请号：US11863231

申请日：2007-09-27

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/745 ,  H01L21/331

CPC classification number: H01L29/7397 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/66348 ,  H01L29/7396

Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

Abstract translation: 具有两个栅极的双栅极IGBT指的是其中第二栅极用于控制空穴电流的阴极。 在导通状态下，可以大大抑制空穴电流。 在切换期间，允许空穴电流流过第二通道。 结合具有预形成的空穴通道的耗尽型p沟道MOSFET，当0V或者低于特定阈值电压的正电压被施加在第二栅极和阴极之间时，其导通的电压不被用于p沟道栅极的负电压 。 通过增加n阱的掺杂和宽度降低碱运输因子，或者通过减少深阱的掺杂降低注入效率，提供通过积极收集的空穴量的主动控制。 器件至少包括阳极，阴极，半导体衬底，n-漂移区，第一和第二栅极，n +阴极区域; p +阴极短，深p阱，n阱和预形成的孔道。

公开(公告)号：US07465964B2

公开(公告)日：2008-12-16

申请号：US11321051

申请日：2005-12-30

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/735

CPC classification number: H01L29/7394 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/402

Abstract: A high voltage/power semiconductor device has a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. Low and high voltage terminals are connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region and a relatively highly doped injector region between the drift region and the high voltage terminal. The device has a relatively highly doped region in electrical contact with the highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.

Abstract translation: 高电压/功率半导体器件具有衬底，衬底上的绝缘层和绝缘层上的半导体层。 低压端子和高压端子连接到半导体层。 该设备具有控制终端。 半导体层包括位于漂移区和高电压端之间的漂移区和相对高掺杂的注入区。 该器件具有与高度掺杂的注入器区域和高电压端子电接触的相对高掺杂的区域，并与衬底形成半导体结。 绝缘层和第一导电类型的相对高掺杂区域的组合有效地将高度掺杂的注入器区域与衬底隔离。

公开(公告)号：US07301220B2

公开(公告)日：2007-11-27

申请号：US11133445

申请日：2005-05-20

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/00

CPC classification number: H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20070158678A1

公开(公告)日：2007-07-12

申请号：US11321051

申请日：2005-12-30

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/74

CPC classification number: H01L29/7394 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/402

Abstract: A high voltage/power semiconductor device has a relatively lowly doped substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer. A low voltage terminal and a high voltage terminal are each electrically connected to the semiconductor layer. The device has a control terminal. The semiconductor layer includes a drift region of a first conductivity type, the substrate being of the second conductivity type. The semiconductor layer includes a relatively highly doped injector region of the second conductivity type between the drift region and the high voltage terminal, said relatively highly doped injector region being in electrical contact with the high voltage terminal and not being connected via any semiconductor layer to the substrate. The device has a relatively highly doped region of the first conductivity type in electrical contact with the said highly doped injector region and the high voltage terminal and forming a semiconductor junction with the substrate. The combination of the insulating layer and the relatively highly doped region of the first conductivity type effectively isolate the highly doped injector region from the substrate.

Abstract translation: 高电压/功率半导体器件具有相对低掺杂的衬底，衬底上的绝缘层和绝缘层上的半导体层。 低电压端子和高电压端子各自电连接到半导体层。 该设备具有控制终端。 半导体层包括第一导电类型的漂移区，该衬底是第二导电类型。 所述半导体层包括位于所述漂移区和所述高电压端之间的所述第二导电类型的相对高度掺杂的注入区，所述相对高掺杂的注入区与所述高压端子电接触，并且不通过任何半导体层连接到 基质。 该器件具有与所述高掺杂的注入器区域和高电压端子电接触并与衬底形成半导体结的第一导电类型的相对高掺杂的区域。 绝缘层和第一导电类型的相对高掺杂区域的组合有效地将高度掺杂的注入器区域与衬底隔离。