公开(公告)号：US07960264B2

公开(公告)日：2011-06-14

申请号：US12901148

申请日：2010-10-08

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/22 ,  H01L21/302

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823437

Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.

Abstract translation: 半导体层的各向异性湿蚀刻产生由沿着半导体层上的电介质硬掩模层中的图案的中心延伸的脊接合的刻面。 去除介电硬掩模层并沉积保形掩模材料层。 通过平行于由脊连接的两个小平面中的Ge，B，Ga，In，As，P，Sb或惰性原子的角度离子注入，导致掩蔽材料层的注入部分的损坏， 屏蔽材料层沿着脊的未损坏部分并且具有恒定的宽度。 在其下面的半导体层和电介质氧化物层对电介质氮化物的其余部分进行蚀刻选择性。 使用电介质氧化物层的剩余部分作为蚀刻掩模，对栅极导体层进行构图以形成具有恒定宽度的栅极导体线。

公开(公告)号：US07943467B2

公开(公告)日：2011-05-17

申请号：US12016317

申请日：2008-01-18

Applicant: Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

Inventor： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

Abstract: A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

Abstract translation: 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

公开(公告)号：US07863169B2

公开(公告)日：2011-01-04

申请号：US11947929

申请日：2007-11-30

Applicant: Huilong Zhu

Inventor： Huilong Zhu

IPC: H01L21/22 ,  H01L21/302

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823437

Abstract: An anisotropic wet etch of a semiconductor layer generates facets joined by a ridge running along the center of a pattern in a dielectric hardmask layer on the semiconductor layer. The dielectric hardmask layer is removed and a conformal masking material layer is deposited. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed parallel to each of the two facets joined by the ridge causing damage to implanted portions of the masking material layer, which are removed selective to undamaged portions of the masking material layer along the ridge and having a constant width. The semiconductor layer and a dielectric oxide layer underneath are etched selective to the remaining portions of the dielectric nitride. Employing remaining portions of the dielectric oxide layer as an etch mask, the gate conductor layer is patterned to form gate conductor lines having a constant width.

公开(公告)号：US07858485B2

公开(公告)日：2010-12-28

申请号：US12191430

申请日：2008-08-14

Applicant: Huilong Zhu ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

Inventor： Huilong Zhu ,  Babar A. Khan ,  Xi Li ,  Joyce C. Liu ,  Thomas A. Wallner

IPC: H01L21/20

CPC classification number: H01L29/66181 ,  H01L27/10861

Abstract: A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.

Abstract translation: 深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。 多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

公开(公告)号：US20100237410A1

公开(公告)日：2010-09-23

申请号：US12407001

申请日：2009-03-19

Applicant: HUILONG ZHU ,  BRUCE B. DORIS ,  PHILIP J. OLDIGES

Inventor： HUILONG ZHU ,  BRUCE B. DORIS ,  PHILIP J. OLDIGES

IPC: H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/26513 ,  H01L29/1045 ,  H01L29/66553 ,  H01L29/66621 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78696

Abstract: A method of forming a semiconductor device is provided that may include providing a semiconductor layer including a raised source and raised drain region that are separated by a recessed channel having a thickness of less than 20 nm, and forming a spacer on a sidewall of the raised source and drain region overlying a portion of the recessed channel. In a following process step, a channel implantation is performed that produces a dopant spike of opposite conductivity as the raised source and drain regions. Thereafter, the offset spacer is removed, and gate structure including a metal gate conductor is formed overlying the recessed channel.

Abstract translation: 提供一种形成半导体器件的方法，其可以包括提供包括由具有小于20nm的厚度的凹陷通道分隔的凸起源和隆起漏极区的半导体层，并且在凸起的顶部的侧壁上形成间隔物 源极和漏极区域覆盖凹陷通道的一部分。 在随后的工艺步骤中，进行沟道注入，其产生具有相反电导率的掺杂尖峰作为升高的源极和漏极区。 此后，去除偏移间隔物，并且包括金属栅极导体的栅极结构形成在凹陷通道上。

公开(公告)号：US07800152B2

公开(公告)日：2010-09-21

申请号：US11835182

申请日：2007-08-07

Applicant: Huilong Zhu ,  Bruce B. Doris

Inventor： Huilong Zhu ,  Bruce B. Doris

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method is provided for producing a fin structure on a semiconductor substrate using a thin SiGe layer to produce a void between a silicon substrate and a silicon fin portion. A fin structure produced by such a method is also provided.

Abstract translation: 提供了一种使用薄SiGe层在半导体衬底上制造鳍结构以在硅衬底和硅片部分之间产生空隙的方法。 还提供了通过这种方法制造的翅片结构。

公开(公告)号：US07791112B2

公开(公告)日：2010-09-07

申请号：US11867264

申请日：2007-10-04

Applicant: Zhjiong Luo ,  Huilong Zhu

Inventor： Zhjiong Luo ,  Huilong Zhu

IPC: H01L21/8238

CPC classification number: H01L21/265 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/517 ,  H01L29/7833 ,  H01L29/7845

Abstract: A method for fabricating a semiconductor structure uses a volumetric change ion implanted into a volumetric change portion of a gate electrode that is located over a channel region within a semiconductor substrate to form a volume changed portion of the gate electrode located over the channel region within the semiconductor substrate. The volume changed portion of the gate electrode is typically bidirectionally symmetrically graded in a vertical direction. The volume-changed portion of the gate electrode has a first stress that induces a second stress different than the first stress into the channel region of the semiconductor substrate.

Abstract translation: 制造半导体结构的方法使用注入到位于半导体衬底内的沟道区域上的栅电极的体积变化部分中的体积变化离子，以形成位于该半导体衬底内的沟道区域上方的栅电极的体积变化部分 半导体衬底。 栅电极的体积变化部分通常在垂直方向上双向对称地分级。 栅电极的体积变化部分具有在半导体衬底的沟道区域中产生不同于第一应力的第二应力的第一应力。

公开(公告)号：US07790581B2

公开(公告)日：2010-09-07

申请号：US11306713

申请日：2006-01-09

Applicant: Byeong Y. Kim ,  Xiaomeng Chen ,  Woo-Hyeong Lee ,  Huilong Zhu

Inventor： Byeong Y. Kim ,  Xiaomeng Chen ,  Woo-Hyeong Lee ,  Huilong Zhu

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/00

CPC classification number: H01L29/1083 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78687

Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.

Abstract translation: 一对半导体结构和半导体结构的制造方法各自使用具有第一晶体取向的半导体衬底和位于其上的电介质层。 该方法提供了在半导体衬底上外延生长半导体层以封装介电层。 该方法还提供了图案化半导体层以产生包括体半导体结构和绝缘体上半导体结构的半导体结构，或者替代地跨越电介质层并接触半导体衬底的图案化半导体层。

公开(公告)号：US07767503B2

公开(公告)日：2010-08-03

申请号：US12132853

申请日：2008-06-04

Applicant: Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

Inventor： Huilong Zhu ,  Philip J. Oldiges ,  Bruce B. Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC: H01L21/84 ,  H01L21/336

CPC classification number: H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract translation: 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US07741658B2

公开(公告)日：2010-06-22

申请号：US11842437

申请日：2007-08-21

Applicant: Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Yaocheng Liu ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L31/0328

CPC classification number: H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

Abstract: The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.

Abstract translation: 本发明的实施例包括自对准超应力p型场效应晶体管（PFET）。 更具体地，场效应晶体管包括包含N掺杂材料的沟道区和沟道区上方的栅。 场效应晶体管还包括在沟道区的第一侧上的源极区域和与第一侧相对的沟道区域的第二侧上的漏极区域。 源极和漏极区域各自包含硅锗，其中硅锗具有外延生长的结构标记。