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    Structure and method to fabricate MOSFET with short gate
    1.
    发明授权
    Structure and method to fabricate MOSFET with short gate 有权
    用短栅制造MOSFET的结构和方法

    公开(公告)号：US07943467B2

    公开(公告)日：2011-05-17

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE
    2.
    发明申请
    STRUCTURE AND METHOD TO MAKE HIGH PERFORMANCE MOSFET WITH FULLY SILICIDED GATE 审中-公开
    具有完全硅胶门的高性能MOSFET的结构和方法

    公开(公告)号：US20090236676A1

    公开(公告)日：2009-09-24

    申请号：US12052069

    申请日：2008-03-20

    申请人： Huilong Zhu ,  Daewon Yang ,  Yanfeng Wang ,  Brian J. Greene

    发明人： Huilong Zhu ,  Daewon Yang ,  Yanfeng Wang ,  Brian J. Greene

    IPC分类号： H01L29/78 ,  H01L21/44

    CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L21/32155 ,  H01L29/4975 ,  H01L29/66507

    摘要： The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor.

    摘要翻译： 本发明在一个实施例中提供了一种制造器件的方法，该器件包括提供包括栅极结构的半导体器件，该栅极结构包括位于衬底顶部的含硅栅极导体; 在至少含硅栅极导体上形成金属层; 并引导化学惰性离子以冲击金属层，其中来自化学惰性离子的动量传递迫使金属原子从金属层进入含硅栅极导体，以提供硅化物栅极导体。

    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE
    3.
    发明申请
    STRUCTURE AND METHOD TO FABRICATE MOSFET WITH SHORT GATE 有权
    具有短栅的MOSFET的结构和方法

    公开(公告)号：US20090184378A1

    公开(公告)日：2009-07-23

    申请号：US12016317

    申请日：2008-01-18

    申请人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    发明人： Huilong Zhu ,  Brian J. Greene ,  Yanfeng Wang ,  Daewon Yang

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L29/7833 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  Y10S257/901

    摘要： A method of producing a semiconducting device is provided that in one embodiment includes providing a semiconducting device including a gate structure atop a substrate, the gate structure including a dual gate conductor including an upper gate conductor and a lower gate conductor, wherein at least the lower gate conductor includes a silicon containing material; removing the upper gate conductor selective to the lower gate conductor; depositing a metal on at least the lower gate conductor; and producing a silicide from the metal and the lower gate conductor. In another embodiment, the inventive method includes a metal as the lower gate conductor.

    摘要翻译： 提供了一种制造半导体器件的方法，其在一个实施例中包括提供包括在衬底顶部的栅极结构的半导体器件，所述栅极结构包括包括上栅极导体和下栅极导体的双栅极导体，其中至少下部 栅极导体包括含硅材料; 去除对下栅极导体选择性的上栅极导体; 在至少所述下栅极导体上沉积金属; 并从金属和下部栅极导体产生硅化物。 在另一个实施例中，本发明的方法包括作为下栅极导体的金属。

    STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES
    6.
    发明申请
    STRESS-GENERATING STRUCTURE FOR SEMICONDUCTOR-ON-INSULATOR DEVICES 有权
    半导体绝缘体器件的应力发生结构

    公开(公告)号：US20120139081A1

    公开(公告)日：2012-06-07

    申请号：US13370898

    申请日：2012-02-10

    申请人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

    发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

    IPC分类号： H01L29/00 ,  H01L21/762

    CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

    摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

    摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

    Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same
    7.
    发明授权
    Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same 有权
    绝缘体上半导体结构，包括含有绝缘体应力插头的沟槽及其制造方法

    公开(公告)号：US08115254B2

    公开(公告)日：2012-02-14

    申请号：US11860851

    申请日：2007-09-25

    申请人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

    发明人： Huilong Zhu ,  Brian J. Greene ,  Dureseti Chidambarrao ,  Gregory G. Freeman

    IPC分类号： H01L27/12

    CPC分类号： H01L29/0603 ,  H01L21/76224 ,  H01L29/1025 ,  H01L29/1054 ,  H01L29/84

    摘要： A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

    摘要翻译： 在绝缘体上半导体（SOI）基板上形成包括第一衬垫氧化物层，衬垫氮化物层和第二焊盘氧化物层的叠层焊盘层。 通过光刻方法和蚀刻形成在SOI衬底的掩埋绝缘体层的顶表面或底表面之下延伸并包围至少一个顶部半导体区域的深沟槽。 应力产生绝缘体材料沉积在深沟槽中并凹陷在SOI衬底的顶表面下方，以在深沟槽中形成应力产生的埋入绝缘体插头。 氧化硅材料沉积在深沟槽中，平坦化和凹陷。 去除衬垫层的堆以暴露顶部半导体层和氧化硅插塞的基本上共面的顶表面。 应力产生埋层绝缘体塞封闭并产生至少一个顶部半导体区域的应力。

    Methods for forming high performance gates and structures thereof
    8.
    发明授权
    Methods for forming high performance gates and structures thereof 失效
    形成高性能栅极的方法及其结构

    公开(公告)号：US07790553B2

    公开(公告)日：2010-09-07

    申请号：US12170687

    申请日：2008-07-10

    申请人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

    发明人： Huilong Zhu ,  Xiaomeng Chen ,  Mahender Kumar ,  Brian J. Greene ,  Bachir Dirahoui ,  Jay W. Strane ,  Gregory G. Freeman

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/82385 ,  H01L21/823857

    摘要： Methods for forming high performance gates in MOSFETs and structures thereof are disclosed. One embodiment includes a method including providing a substrate including a first short channel active region, a second short channel active region and a long channel active region, each active region separated from another by a shallow trench isolation (STI); and forming a field effect transistor (FET) with a polysilicon gate over the long channel active region, a first dual metal gate FET having a first work function adjusting material over the first short channel active region and a second dual metal gate FET having a second work function adjusting material over the second short channel active region, wherein the first and second work function adjusting materials are different.

    摘要翻译： 公开了在MOSFET中形成高性能栅极的方法及其结构。 一个实施例包括提供包括第一短沟道有源区，第二短沟道有源区和长沟道有源区的衬底的方法，每个有源区通过浅沟槽隔离（STI）与另一个分离。 以及在所述长沟道有源区上形成具有多晶硅栅极的场效应晶体管（FET），在所述第一短沟道有源区上具有第一功函数调节材料的第一双金属栅极FET和具有第二双金属栅极FET的第二双金属栅极FET， 第二短通道有源区域上的功函数调整材料，其中第一和第二功函数调节材料不同。