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    DISCHARGE PHASE CHANGE MATERIAL MEMORY
    81.
    发明申请
    DISCHARGE PHASE CHANGE MATERIAL MEMORY 审中-公开
    放电相变材料存储器

    公开(公告)号：US20100165726A1

    公开(公告)日：2010-07-01

    申请号：US12650676

    申请日：2009-12-31

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: G11C11/00 ,  G11C7/00

    CPC classification number: G11C13/0007 ,  G11C13/0004 ,  G11C13/0038 ,  G11C27/024 ,  G11C2213/31

    Abstract: An information storage array includes a programmable material at a storage location and a capacitor set. A switching network charges the capacitor set to a first voltage and discharges the capacitor set at a second voltage. The second voltage is greater than the first voltage and it or a waveform derived therefrom is applied to the storage location to thereby change a state of the programmable material.

    Abstract translation: 信息存储阵列包括存储位置处的可编程材料和电容器组。 开关网络将电容器设置为第一电压，并将电容器组放电为第二电压。 第二电压大于第一电压，并将其或由其导出的波形施加到存储位置，从而改变可编程材料的状态。

    LOW-VOLUME PHASE-CHANGE MATERIAL MEMORY CELL
    82.
    发明申请
    LOW-VOLUME PHASE-CHANGE MATERIAL MEMORY CELL 审中-公开
    低体积相变材料存储单元

    公开(公告)号：US20100163836A1

    公开(公告)日：2010-07-01

    申请号：US12643278

    申请日：2009-12-21

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: H01L45/00 ,  H01L21/20

    CPC classification number: H01L45/1691 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144

    Abstract: A memory device includes a memory array comprising a plurality of storage locations disposed above a plurality of generally parallel lines, where each storage location comprises a programmable material disposed on a sidewall of a conductive element.

    Abstract translation: 存储器件包括存储器阵列，该存储器阵列包括设置在多个大致平行线上的多个存储位置，其中每个存储位置包括设置在导电元件的侧壁上的可编程材料。

    Sequencing Decoder Circuit
    84.
    发明申请
    Sequencing Decoder Circuit 有权
    排序解码电路

    公开(公告)号：US20100085830A1

    公开(公告)日：2010-04-08

    申请号：US12575055

    申请日：2009-10-07

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: G11C8/10 ,  G11C8/04

    CPC classification number: G11C8/10

    Abstract: A memory-array decoder operably coupled to a memory array comprising a sequence of rows and receiving as input a plurality of address bits includes first and second decoder stages. The first decoder stage selects one or more first rows by decoding a first subset of the address bits, and the second decoder stage selects one or more second rows based on locations, within the sequence, of one or more third rows different from the one or more second rows.

    Abstract translation: 可操作地耦合到存储器阵列的存储器阵列解码器，该存储器阵列包括一系列行并作为输入接收多个地址位，包括第一和第二解码器级。 第一解码器级通过解码地址位的第一子集来选择一个或多个第一行，并且第二解码器级基于序列内的与一个或多个第三行不同的一个或多个第三行中的位置来选择一个或多个第二行， 更多第二排。

    Nano-vacuum-tubes and their application in storage devices
    85.
    发明授权
    Nano-vacuum-tubes and their application in storage devices 有权
    纳米真空管及其在存储设备中的应用

    公开(公告)号：US07667996B2

    公开(公告)日：2010-02-23

    申请号：US11707739

    申请日：2007-02-15

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: G11C11/30

    CPC classification number: G11C17/06 ,  G11C17/14 ,  H01L27/1021 ,  Y10S977/939

    Abstract: The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.

    Abstract translation: 通过将存储阵列中的基于半导体的二极管改变为冷阴极，基于场发射器的器件，二极管阵列存储器件中器件的规模及其成本得以降低。 场发射器和场发射器阵列可以使用基于地形的光刻技术来制造。

    SCR matrix storage device
    86.
    发明授权
    SCR matrix storage device 有权
    SCR矩阵存储设备

    公开(公告)号：US07652916B2

    公开(公告)日：2010-01-26

    申请号：US12107500

    申请日：2008-04-22

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: G11C11/36 ,  G11C11/34

    CPC classification number: G11C17/06 ,  Y10T29/49002

    Abstract: One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others.

    Abstract translation: 数据存储设备的最简单形式之一是二极管阵列存储设备。 然而，二极管阵列存储器件的问题在于，随着阵列的尺寸增加，连接在阵列的给定选定行或列之间的非寻址二极管的数量和阵列的未寻址列或行的数量分别为 ，也变得非常大。 虽然通过所选行或列上的任何一个非寻址二极管的漏电流对器件的操作几乎没有影响，但通过数千个非寻址二极管的累积泄漏可能变得显着。 该累积漏电流可以变得足够大，使得可以移位输出电压，使得用于区分寻址二极管位置的一个状态和零状态的阈值可能变得模糊，并且可能导致寻址的二极管位置的误读。 本发明是一种管理二极管阵列存储装置中的漏电流的手段。 这是通过主动地改变存储阵列中的二极管的正向电压来实现的，使得连接到所选行线但不连接到所选列线的二极管处于其高阻抗状态，并且连接到所选列的二极管 但是没有连接到所选择的行线处于其高阻抗状态; 只有连接到所选行线和所选列线的二极管将切换到其低阻抗状态。 本发明是对所有类型的二极管阵列或其它非线性导电元件的阵列的增强，包括：存储设备，可编程逻辑器件，显示阵列，传感器阵列等等。

    DIODE DECODER ARRAY WITH NON-SEQUENTIAL LAYOUT AND METHODS OF FORMING THE SAME
    87.
    发明申请
    DIODE DECODER ARRAY WITH NON-SEQUENTIAL LAYOUT AND METHODS OF FORMING THE SAME 审中-公开
    具有非顺序布局的二极管解码器阵列及其形成方法

    公开(公告)号：US20090296445A1

    公开(公告)日：2009-12-03

    申请号：US12476525

    申请日：2009-06-02

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: G11C5/02 ,  H01S4/00 ,  G11C8/10

    CPC classification number: G11C8/10 ,  G11C5/063 ,  Y10T29/49002

    Abstract: In various embodiments, an electronic circuit includes an array of locations each corresponding to an intersection of a row and a column, and a plurality of devices each disposed proximate one of the locations, wherein no more than ten contiguous locations lack a proximate device.

    Abstract translation: 在各种实施例中，电子电路包括每个对应于行和列的交叉点的位置阵列，以及各个设置在每个位置附近的多个设备，其中不超过十个连续的位置缺少邻近的设备。

    Fabrication of semiconductor devices
    89.
    发明授权
    Fabrication of semiconductor devices 有权

    公开(公告)号：US07507663B2

    公开(公告)日：2009-03-24

    申请号：US11655470

    申请日：2007-01-19

    Applicant: Daniel R. Shepard

    Inventor： Daniel R. Shepard

    IPC: H01L21/44

    CPC classification number: H01L27/1203 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/101 ,  H01L27/1214

    Abstract: Fabrication of microelectronic devices is accomplished using a substrate having a recessed pattern. In one approach, a master form is used to replicate a substrate having a pit pattern. In another approach, the substrate is produced by etching. A series of stacked layers having desired electrical characteristics is applied to the substrate and planarized in a manner that creates electrical devices and connections therebetween. The microelectronic devices can include a series of row and columns and are used to store data at their intersection.

    Deferred acknowledgment communications and alarm management
    90.
    发明授权
    Deferred acknowledgment communications and alarm management 有权
    延期确认通讯和报警管理

    公开(公告)号：US06775707B1

    公开(公告)日：2004-08-10

    申请号：US09418747

    申请日：1999-10-15

    Applicant: William E. Bennett ,  Ken J. Beoughter ,  Robert B. Havekost ,  John R. Shepard ,  Dwight D. Jennings

    Inventor： William E. Bennett ,  Ken J. Beoughter ,  Robert B. Havekost ,  John R. Shepard ,  Dwight D. Jennings

    IPC: G06F1516

    CPC classification number: H04L47/27 ,  H04B7/18593 ,  H04L1/1685 ,  H04L1/188 ,  H04L1/1887 ,  H04L47/10 ,  H04L47/14 ,  H04L47/283 ,  H04L69/324

    Abstract: A communication technique enables the efficient transmission of data through a low bandwidth and/or time delayed communication link and minimizes the idle time of the communication link by using a deferred acknowledgment of message bundles to temporally pack the communication link. The transmitting system stores messages to be transmitted in a pending message queue and applies a dynamic window to the pending message queue to define a message bundle to be sent through the slow communication link. The transmitting system requests an acknowledgment for at least one message within the bundle, but does not require an acknowledgment for every message within the bundle. Transmitted messages are temporarily stored as outstanding messages in a retransmission queue until the transmitted messages are acknowledged or until a time-out period associated with the messages has lapsed. When the transmitting station receives a timely acknowledgment in response to a requested acknowledgment, the transmitting station removes all outstanding messages associated with that acknowledgment from the retransmission queue.

    Abstract translation: 通信技术能够通过低带宽和/或时间延迟的通信链路有效地传输数据，并且通过使用消息束的延迟确认来最小化通信链路的空闲时间，以暂时包装通信链路。 发送系统存储要在待定消息队列中发送的消息，并将动态窗口应用于待定消息队列，以定义要通过慢速通信链路发送的消息包。 发送系统向捆绑中的至少一个消息请求确认，但不需要对捆绑内的每个消息进行确认。 传输的消息作为未完成的消息临时存储在重传队列中，直到发送的消息被确认或直到与消息相关联的超时周期已经失效。 当发送站响应于所请求的确认接收到及时确认时，发送站从重发队列中删除与该确认相关联的所有未完成的消息。

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