公开(公告)号：US11271537B2

公开(公告)日：2022-03-08

申请号：US16410437

申请日：2019-05-13

Applicant: SOCIONEXT INC.

Inventor： Atheer Sami Barghouthi ,  Saul Darzy

IPC: H03H7/00 ,  H02H9/04 ,  H03H7/01

Abstract: An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side of the signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the auxillary pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

公开(公告)号：US11249179B2

公开(公告)日：2022-02-15

申请号：US16939884

申请日：2020-07-27

Applicant: SOCIONEXT INC.

Inventor： Kiichi Hamasaki ,  Masato Suzuki

IPC: G01S13/62 ,  G01S13/87

Abstract: A motion detection system includes a first motion detection device that detects a motion of an object based on a reflected wave of a radio wave transmitted by a first radio wave sensor, the first motion detection device including the first radio wave sensor, and a second motion detection device that detects the motion based on a reflected wave of a radio wave transmitted by a second radio wave sensor, the second motion detection device including the second radio wave sensor, wherein one motion detection device among the first and second motion detection devices transmits a determination radio wave and another motion detection device among the first and second motion detection devices receives the determination radio wave, and wherein only the first motion detection device is used to detect the motion when received intensity of the received determination radio wave is smaller than a predetermined threshold.

公开(公告)号：US20220038090A1

公开(公告)日：2022-02-03

申请号：US17370453

申请日：2021-07-08

Applicant: SOCIONEXT INC.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN ,  Ricardo DOLDAN LORENZO

IPC: H03K17/16 ,  G05F1/46

Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.

公开(公告)号：US11197011B2

公开(公告)日：2021-12-07

申请号：US17032446

申请日：2020-09-25

Applicant: Socionext Inc.

Inventor： Hirofumi Nagaoka

IPC: H04N19/137 ,  H04N19/159 ,  H04N19/176 ,  H04N19/44 ,  H04N19/105 ,  H04N19/51

Abstract: A decoding method includes obtaining a rectangular region to be decoded in a picture, setting a first template region in accordance with a position of the rectangular region, setting a second template region corresponding to the first template region in a reference picture, setting third template regions each of which is obtained by moving the second template region using a corresponding vector in the reference picture, calculating image correlation values each of which is obtained between a corresponding one of the third template regions and the first template region, determining a motion vector of the rectangular region, wherein the setting a first template region includes setting a region adjacent to a predetermined block including the rectangular region as the first template region when a size of the rectangular region is a predetermined threshold size or smaller, or when a picture including the rectangular region corresponds to a non-reference picture.

公开(公告)号：US20210344345A1

公开(公告)日：2021-11-04

申请号：US17244821

申请日：2021-04-29

Applicant: SOCIONEXT INC.

Inventor： Osamu UNO

IPC: H03K19/094 ,  H03K19/0185 ,  H03K17/687

Abstract: An input circuit includes an input buffer circuit using a first node as an input and a second node as an output, an N-type transistor having a source coupled to the input terminal, a drain coupled to the first node, and a gate coupled to a power supply, and a pull-up circuit provided between the first node and the power supply. The pull-up circuit is configured to make the power supply and the first node conducive with each other for a predetermined period when the input signal transitions from low to high and not to make the power supply and the first node conductive with each other when the input signal transitions from high to low.

公开(公告)号：US20210335774A1

公开(公告)日：2021-10-28

申请号：US17370912

申请日：2021-07-08

Applicant: SOCiONEXT INC.

Inventor： Hironobu OCHIAI

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522

Abstract: Between strap power supply lines that supply a power supply potential VDD, standard cell columns and standard cell columns are arranged alternately in a Y-direction. Out of capacitor cells and correction cells, only the capacitor cells are arranged in the standard cell columns, and only the correction cells are arranged in the standard cell columns.

公开(公告)号：US20210320065A1

公开(公告)日：2021-10-14

申请号：US17357211

申请日：2021-06-24

Applicant: SOCIONEXT INC.

Inventor： Koshiro DATE

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423

Abstract: An inverter cell having a logical function and a filler cell having no logical function are placed adjacent to each other. Nanowires of the filler cell are placed at the same positions as nanowires of the inverter cell in the Y direction. A p-type dummy transistor and n-type dummy transistor of the filler cell are respectively placed at the same levels as a p-type transistor and n-type transistor of the inverter cell in the Z direction.

公开(公告)号：US20210281266A1

公开(公告)日：2021-09-09

申请号：US17327358

申请日：2021-05-21

Applicant: SOCIONEXT INC.

Inventor： Yoji Bando ,  Heiji IKOMA

IPC: H03L7/099 ,  H03K3/03 ,  H03L7/089

Abstract: A voltage-controlled oscillator includes: a first transistor with its gate connected to an input terminal, its source connected to a first power supply, and its drain connected to a first node; a second transistor with its gate connected to a first bias voltage, its source connected to a second power supply, and its drain connected to the first node; and an inverter ring connected between the first node and the first power supply. The inverter ring is constituted by a plurality of stages of inverters connected in series, and an output of a final-stage inverter is connected to an output terminal and an input of an initial-stage inverter.

公开(公告)号：US20210242242A1

公开(公告)日：2021-08-05

申请号：US17235603

申请日：2021-04-20

Applicant: SOCIONEXT INC.

Inventor： Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118 ,  H01L29/423 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/06 ,  H01L27/092 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

公开(公告)号：US20210241817A1

公开(公告)日：2021-08-05

申请号：US17211552

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: G11C11/408 ,  G11C11/4094 ,  G11C5/06

Abstract: A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.