公开(公告)号：US06985382B2

公开(公告)日：2006-01-10

申请号：US10973720

申请日：2004-10-26

申请人： David E. Fulkerson ,  Yong Lu

发明人： David E. Fulkerson ,  Yong Lu

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A technique to read a stored state in a magnetoresistive random access memory (MRAM) device, such as a giant magneto-resistance (GMR) MRAM device or a tunneling magneto-resistance (TMR) device uses a bit line in an MRAM device that is segmented into a first portion and a second portion. An interface circuit compares the resistance of a first portion and a second portion of a first bit line to the resistance of a first portion and a second portion of a second bit line to determine the logical state of a cell in the first bit line. The interface circuit includes a reset circuit that selectively couples the outputs of the interface circuit together. A subsequent decoupling of the outputs allows cross-coupling within the interface circuit to latch the outputs to a logical state corresponding to the stored magnetic state, thereby allowing the stored state of a cell to be read.

摘要翻译： 在诸如巨磁电阻（MRM）MRAM装置或隧道磁阻（TMR）装置的磁阻随机存取存储器（MRAM）装置中读取存储状态的技术使用MRAM装置中的位线 分割成第一部分和第二部分。 接口电路将第一位线的第一部分和第二部分的电阻与第二位线的第一部分和第二部分的电阻进行比较，以确定第一位线中的单元的逻辑状态。 接口电路包括将接口电路的输出选择性地耦合在一起的复位电路。 输出的随后的去耦允许接口电路内的交叉耦合以将输出锁存到对应于存储的磁状态的逻辑状态，从而允许读取单元的存储状态。

公开(公告)号：US06972988B1

公开(公告)日：2005-12-06

申请号：US10637145

申请日：2003-08-08

申请人： Yong Lu ,  Romney R. Katti

发明人： Yong Lu ,  Romney R. Katti

IPC分类号： G11C5/14 ,  G11C11/00 ,  G11C11/16

CPC分类号： G11C5/14 ,  G11C5/144 ,  G11C11/16 ,  Y10T307/527

摘要： The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated giant-magneto-resistive (GMR) structures. A non-volatile logic state retention devices, such as GMR storage elements, and concerns a save-on-power-down circuit that may be integrated with conventional semiconductor-based computing, logic, and memory devices to retain volatile logic states and/or volatile digital information in a non-volatile manner.

摘要翻译： 半导体行业旨在通过改进的非易失性存储设备降低传统易失性存储设备的风险。 对于显着提升，高效和非易失性数据保留技术的需求的增加推动了集成的巨磁阻（GMR）结构的发展。 非易失性逻辑状态保持装置，例如GMR存储元件，并且涉及可以与常规的基于半导体的计算，逻辑和存储器装置集成的保存在掉电电路以保持易失性逻辑状态和/或 不稳定的数字信息。

公开(公告)号：US06765820B2

公开(公告)日：2004-07-20

申请号：US10352278

申请日：2003-01-27

申请人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

发明人： Yong Lu ,  Theodore Zhu ,  Romney R. Katti

IPC分类号： G11C1100

CPC分类号： G11C11/5607 ,  G11C7/06 ,  G11C11/15

摘要： A low power, high speed magneto-resistive memory is disclosed. The disclosed memory directly senses the resistive state of one or more magneto-resistive memory elements. This allows the memory to be read during a single read cycle, without the need for a word line current. This may substantially increase the speed and reduce the power of the memory.

摘要翻译： 公开了一种低功率高速磁阻存储器。 所公开的存储器直接感测一个或多个磁阻存储元件的电阻状态。 这允许在单个读取周期期间读取存储器，而不需要字线电流。 这可能会显着增加速度并降低存储器的功率。

公开(公告)号：US06735112B2

公开(公告)日：2004-05-11

申请号：US10068465

申请日：2002-02-06

申请人： Theodore Zhu ,  Yong Lu ,  Anthony Arrott

发明人： Theodore Zhu ,  Yong Lu ,  Anthony Arrott

IPC分类号： G11C1115

CPC分类号： G11C11/16 ,  G11C11/15

摘要： A magneto-resistive memory comprising magneto-resistive memory cells is disclosed, comprising two pinned magnetic layers on one side of a free magnetic layer. The pinned magnetic layers are formed with anti-parallel magnetization orientations such that a net magnetic moment of the two layers is substantially zero. The influence of pinned magnetic layers on free magnetic layer magnetization orientations is substantially eliminated, allowing for increased predictability in switching behavior and increased write selectivity of memory cells.

摘要翻译： 公开了包括磁阻存储器单元的磁阻存储器，其包括在自由磁性层的一侧上的两个固定磁性层。 被钉扎的磁性层形成为具有反平行磁化取向，使得两层的净磁矩基本为零。 固有磁性层对自由磁性层磁化取向的影响基本上消除了，从而增加了开关行为的可预测性和增加了存储单元的写入选择性。

公开(公告)号：US06671834B1

公开(公告)日：2003-12-30

申请号：US09618492

申请日：2000-07-18

申请人： Theodore Zhu ,  Gary Kirchner ,  Richard W. Swanson ,  Yong Lu

发明人： Theodore Zhu ,  Gary Kirchner ,  Richard W. Swanson ,  Yong Lu

IPC分类号： G11C2900

CPC分类号： G11C29/808 ,  G11C29/846

摘要： A redundancy scheme for a memory is disclosed that is programmable both before and after the memory device is packaged and/or installed in a system. This is preferably accomplished by using programmable non-volatile memory elements to control the replacement circuitry. Because the programmable memory elements are non-volatile, the desired replacement configuration is not lost during shipping, or if power is lost in a system. By allowing post-packaging replacement of defective memory elements, the overall yield of the device may be improved. By allowing post system installation replacement of defective memory elements, the reliability of many systems may be improved. In addition, the disclosed redundancy scheme allows two or more defective memory elements from different rows or columns to be replaced with memory elements from a single redundant low or column. This provides added flexibility during the replacement process.

摘要翻译： 公开了一种用于存储器的冗余方案，其在存储器件被封装和/或安装在系统中之前和之后是可编程的。 这优选地通过使用可编程非易失性存储器元件来控制替换电路来实现。 由于可编程存储器元件是非易失性的，所以在运输过程中，或者系统中的电源丢失时，所需的更换配置不会丢失。 通过允许更换缺陷存储元件的后期封装，可以提高器件的整体产量。 通过允许后置系统安装更换有缺陷的存储器元件，可以提高许多系统的可靠性。 此外，所公开的冗余方案允许来自不同行或列的两个或更多个有缺陷的存储器元件被来自单个冗余低或列的存储器元件替换。 这在更换过程中提供了更多的灵活性。

公开(公告)号：US06590805B2

公开(公告)日：2003-07-08

申请号：US10293797

申请日：2002-11-12

申请人： Yong Lu ,  Michael F. Dries

发明人： Yong Lu ,  Michael F. Dries

IPC分类号： G11C1115

CPC分类号： G11C11/15

摘要： A magneto-resistive memory is disclosed that includes a high-speed sense amplifier, that can reliably operate at low signal levels. The sense amplifier includes offset cancellation to reduce or eliminate the internal offsets of the amplifier. The offset cancellation is controlled by one or more switches, which during operation, selectively enable the offset cancellation of the amplifier and store the offsets in one or more coupling capacitors.

摘要翻译： 公开了一种磁阻存储器，其包括可在低信号电平下可靠地工作的高速读出放大器。 读出放大器包括偏移消除以减少或消除放大器的内部偏移。 偏移消除由一个或多个开关控制，在操作期间，选择性地启用放大器的偏移消除并将偏移存储在一个或多个耦合电容器中。

公开(公告)号：US06424564B1

公开(公告)日：2002-07-23

申请号：US09964217

申请日：2001-09-26

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C1100

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

公开(公告)号：US06424561B1

公开(公告)日：2002-07-23

申请号：US09618504

申请日：2000-07-18

申请人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

发明人： Shaoping Li ,  Theodore Zhu ,  Anthony S. Arrott ,  Harry Liu ,  William L. Larson ,  Yong Lu

IPC分类号： G11C1100

CPC分类号： G11C11/16 ,  G11C11/15 ,  H01L27/222

摘要： MRAM architectures are disclosed that produce an increased write margin and write selectivity without significantly reducing the packing density of the memory. The major axes of the magneto-resistive bits are offset relative to the axes of the digital lines to produce a magnetic field component from the digital line current that extends along the major axis of the magneto-resistive bits.

摘要翻译： 公开了在不显着降低存储器的封装密度的情况下产生增加的写入裕度和写入选择性的MRAM架构。 磁阻位的主轴相对于数字线的轴线偏移，以从沿着磁阻位的长轴延伸的数字线电流产生磁场分量。

公开(公告)号：US06134138A

公开(公告)日：2000-10-17

申请号：US365308

申请日：1999-07-30

申请人： Yong Lu ,  Theodore Zhu

发明人： Yong Lu ,  Theodore Zhu

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00

CPC分类号： G11C11/16

摘要： A method and apparatus for reading a magnetoresistive memory is disclosed wherein the wordline current is turned off during selected sensing operations. This substantially eliminates the noise that is typically injected by the wordline current into the bit structures during the sensing operations, which increases the signal-to-noise ratio on the sense lines. This, in turn, significantly increases the speed of the sensing operations and thus the read access time of the memory. Substantial power savings are also realized.

摘要翻译： 公开了一种用于读取磁阻存储器的方法和装置，其中在所选择的感测操作期间，字线电流被关断。 这实质上消除了在感测操作期间通常由字线电流注入到位结构中的噪声，这增加了感测线上的信噪比。 这反过来显着增加了感测操作的速度，从而显着提高了存储器的读取访问时间。 也实现了大量的省电。

公开(公告)号：US20170127153A1

公开(公告)日：2017-05-04

申请号：US15407433

申请日：2017-01-17

申请人： Yong LU

发明人： Yong LU

IPC分类号： H04N21/854 ,  H04N21/81 ,  H04N21/2665 ,  H04N21/258 ,  H04N21/218 ,  H04N21/2187

CPC分类号： H04N21/854 ,  H04N21/21805 ,  H04N21/2187 ,  H04N21/222 ,  H04N21/25808 ,  H04N21/25866 ,  H04N21/2665 ,  H04N21/8106

摘要： Embodiments of present invention provide a method and system for collecting, transmitting, editing and integrating, broadcasting, and receiving signals. The method comprises acquiring one and/or more audio signals and one and/or more video signals for the one program collected by one and/or more audio and video collection terminals; editing and integrating the one and/or more audio signals and the one and/or more video signals for the one program on a network platform, and then broadcasting; selecting among the one and/or more audio signals and the one and/or more video signals for the one program at a receiving terminal, and receiving the selected audio signal and video signal.