公开(公告)号：US09484113B2

公开(公告)日：2016-11-01

申请号：US14253638

申请日：2014-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F11/00 ,  G11C29/04 ,  G06F11/10 ,  G11C11/16

CPC classification number: G11C29/04 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.

Abstract translation: 存储器读取操作指向已经从其移除第一半导体器件的一组半导体器件。 基于纠错编码（ECC）检测存储器读取操作的数据中的错误。 该误差至少部分地由第一半导体器件被去除。 ECC用于确定用于存储器读取操作的校正数据。

公开(公告)号：US20160147467A1

公开(公告)日：2016-05-26

申请号：US14554972

申请日：2014-11-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G06F12/0238 ,  G06F2212/7211

Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.

Abstract translation: 在一种形式中，数据处理器包括存储器访问代理和存储器控制器。 存储器访问代理选择性地启动对存储器的读访问和写存取。 存储器控制器耦合到存储器访问代理，并且适于被耦合到存储器并且使用起始间隙损耗均衡算法访问存储器。 存储器控制器适于将元数据日志维护在存储器的区域中，并且在元数据日志中存储起始地址损耗均衡算法中使用的起始地址和间隙地址，并且在初始化时将元数据日志访问到 检索在起始间隙磨损均衡算法中使用的初始起始地址和初始间隙地址。 在另一形式中，存储器模块可以包括包括这种存储器控制器的存储器缓冲器。

公开(公告)号：US20150302937A1

公开(公告)日：2015-10-22

申请号：US14257919

申请日：2014-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski

IPC: G11C29/00 ,  G11C7/00 ,  G11C11/56

CPC classification number: G11C16/3418 ,  G11C11/56 ,  G11C11/5642 ,  G11C13/0033 ,  G11C13/004

Abstract: A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. The memory cell is reprogrammed to mitigate an offset between the parameter as measured with the second resolution and the parameter as measured with the first resolution.

Abstract translation: 通过用第一分辨率测量与存储器单元相关联的参数来读取存储单元，以确定存储在存储单元中的值。 该参数也用比第一分辨率更精细的第二分辨率来测量。 重新编程存储器单元以减轻用第二分辨率测量的参数与用第一分辨率测量的参数之间的偏移。

公开(公告)号：US20150186075A1

公开(公告)日：2015-07-02

申请号：US14146618

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G06F13/16 ,  Y02D10/14

Abstract: A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.

Abstract translation: 存储器装置并行地接收多个读取命令和/或写入命令。 存储器件在数据总线的相应部分上发送与各个读取命令对应的数据，并且在数据总线的相应部分上接收对应于各个写命令的数据。 存储器件包括并行接收多个读取命令的I / O逻辑，以在数据总线的相应部分上发送对应于相应读取命令的数据，并且在相应部分上接收对应于各个写入命令的数据 的数据总线。

公开(公告)号：US12080362B2

公开(公告)日：2024-09-03

申请号：US18154372

申请日：2023-01-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Steven Raasch ,  Greg Sadowski ,  David A. Roberts

IPC: G11C16/34 ,  G06F3/06 ,  G06F9/50 ,  G06F12/02 ,  G11C7/04 ,  G11C11/4076 ,  G11C29/00

CPC classification number: G11C16/3495 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F9/50 ,  G06F12/0223 ,  G06F12/0246 ,  G11C7/04 ,  G11C11/4076 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/70 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.

公开(公告)号：US11347650B2

公开(公告)日：2022-05-31

申请号：US15891322

申请日：2018-02-07

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Elliot H. Mednick

IPC: G06F12/0895 ,  G06F3/06 ,  G06F12/06

Abstract: A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.

公开(公告)号：US11294747B2

公开(公告)日：2022-04-05

申请号：US15884638

申请日：2018-01-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06F11/07 ,  G06N5/04 ,  G06N3/02 ,  G06K9/03 ,  G06N20/00

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

公开(公告)号：US11165749B2

公开(公告)日：2021-11-02

申请号：US15043212

申请日：2016-02-12

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: H04L29/12 ,  H04L12/741 ,  H04L12/753 ,  H04L29/06

Abstract: A controller assigns variable length addresses to addressable elements that are connected to a network. The variable length addresses are determined based on probabilities that packets are addressed to the corresponding addressable element. The controller transmits, to the addressable elements via the network, a routing table indicating the variable length addresses assigned to the addressable elements. Routers or addressable elements receive the routing table and route one or more packets over the network to an addressable element using variable length addresses included in a header of the one or more packets.

公开(公告)号：US10990453B2

公开(公告)日：2021-04-27

申请号：US15952149

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F9/52

Abstract: A memory fence or other similar operation is executed with reduced latency. An early fence operation is executed and acts as a hint to the processor executing the thread that executes the fence. This hint causes the processor to begin performing sub-operations for the fence earlier than if no such hint were executed. Examples of sub-operations for the fence include operations to make data written to by writes prior to the fence operation available to other threads. A resolving fence, which occurs after the early fence, performs the remaining sub-operations for the fence. By triggering some or all of the sub-operations for a memory fence that will occur in the future, the early fence operation reduces the amount of latency associated with that memory fence operation.

公开(公告)号：US10970118B2

公开(公告)日：2021-04-06

申请号：US15974014

申请日：2018-05-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06F9/46 ,  G06F9/50 ,  G06F15/78 ,  G06F9/52

Abstract: Systems, apparatuses, and methods for sharing an field programmable gate array compute engine are disclosed. A system includes one or more processors and one or more FPGAs. The system receives a request, generated by a first user process, to allocate a portion of processing resources on a first FPGA. The system maps the portion of processing resources of the first FPGA into an address space of the first user process. The system prevents other user processes from accessing the portion of processing resources of the first FPGA. Later, the system detects a release of the portion of the processing resources on the first FPGA by the first user process. Then, the system receives a second request to allocate the first FPGA from a second user process. In response to the second request, the system maps the first FPGA into an address space of the second user process.