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公开(公告)号：US11551990B2
公开(公告)日：2023-01-10
申请号：US15674607
申请日：2017-08-11
发明人： David A. Roberts , Greg Sadowski , Steven Raasch
IPC分类号： H01L23/34 , G05B15/02 , H01L25/065 , G06F1/20
摘要： Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号：US20210191797A1
公开(公告)日：2021-06-24
申请号：US16723855
申请日：2019-12-20
IPC分类号： G06F11/07 , G06F11/10 , G06F9/30 , G06F13/16 , G11C11/409
摘要： A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.
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公开(公告)号：US12080362B2
公开(公告)日：2024-09-03
申请号：US18154372
申请日：2023-01-13
发明人： Steven Raasch , Greg Sadowski , David A. Roberts
CPC分类号： G11C16/3495 , G06F3/0616 , G06F3/064 , G06F3/0679 , G06F9/50 , G06F12/0223 , G06F12/0246 , G11C7/04 , G11C11/4076 , G11C16/3418 , G11C16/349 , G11C29/70 , G06F2212/1036 , G06F2212/7211
摘要： Exemplary embodiments provide wear spreading among die regions (i.e., one or more circuits) in an integrated circuit or among dies by using operating condition data in addition to or instead of environmental data such as temperature data, from each of a plurality of die regions. Control logic produces a cumulative amount of time each of the plurality of die regions has spent at an operating condition based on operating condition data wherein the operating condition data is based on at least one of the following operating characteristics: frequency of operation of the plurality of die regions, an operating voltage of the plurality of die regions, an activity level of the plurality of die regions, a timing margin of the plurality of die regions, and a number of detected faults of the plurality of die regions. The method and apparatus spreads wear among the plurality of same type of die regions by controlling task execution among the plurality of die regions using the die wear-out data.
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公开(公告)号：US11816037B2
公开(公告)日：2023-11-14
申请号：US16712129
申请日：2019-12-12
发明人： Steven Raasch , Andrew G. Kegel
IPC分类号： G06F12/10 , G06F12/1009 , G06F12/1027 , G06F12/123 , G06F9/50 , G06F12/0871 , G06F12/02 , G06F11/07 , G06F12/0882
CPC分类号： G06F12/1009 , G06F9/5016 , G06F11/0772 , G06F12/0246 , G06F12/0871 , G06F12/0882 , G06F12/1027 , G06F12/123
摘要： A processing system includes a primary processor and a co-processor. The primary processor is couplable to a memory subsystem having at least one memory and operating to execute system software employing memory address translations based on one or more page tables stored in the memory subsystem. The co-processor is likewise couplable to the memory subsystem and operates to perform iterations of a page table walk through one or more page tables maintained for the memory subsystem and to perform one or more page management operations on behalf of the system software based the iterations of the page table walk. The page management operations performed by the co-processor include analytic data aggregation, free list management and page allocation, page migration management, page table error detection, and the like.
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公开(公告)号：US20190051576A1
公开(公告)日：2019-02-14
申请号：US15674607
申请日：2017-08-11
发明人： David A. Roberts , Greg Sadowski , Steven Raasch
IPC分类号： H01L23/34 , H01L25/065 , G05B15/02
摘要： Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号：US11586539B2
公开(公告)日：2023-02-21
申请号：US16713940
申请日：2019-12-13
IPC分类号： G06F12/08 , G06F12/0811 , G06F12/0871 , G06F9/30 , G06F12/0882 , G06F12/1027 , G06F12/0831
摘要： A processing system selectively allocates space to store a group of one or more cache lines at a cache level of a cache hierarchy having a plurality of cache levels based on memory access patterns of a software application executing at the processing system. The processing system generates bit vectors indicating which cache levels are to allocate space to store groups of one or more cache lines based on the memory access patterns, which are derived from data granularity and movement information. Based on the bit vectors, the processing system provides hints to the cache hierarchy indicating the lowest cache level that can exploit the reuse potential for a particular data.
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7.发明授权公开(公告)号：US10365996B2
公开(公告)日：2019-07-30
申请号：US15331270
申请日：2016-10-21
发明人： Manish Gupta , David A. Roberts , Mitesh R. Meswani , Vilas Sridharan , Steven Raasch , Daniel I. Lowell
摘要： Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.
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公开(公告)号：US12068215B2
公开(公告)日：2024-08-20
申请号：US18152022
申请日：2023-01-09
发明人： David A. Roberts , Greg Sadowski , Steven Raasch
IPC分类号： H01L23/34 , G05B15/02 , G06F1/20 , H01L25/065
CPC分类号： H01L23/34 , G05B15/02 , G06F1/20 , H01L25/0657 , H01L2225/06589
摘要： Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.
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公开(公告)号：US12066965B2
公开(公告)日：2024-08-20
申请号：US16863149
申请日：2020-04-30
CPC分类号： G06F13/4027 , G06F13/4282 , H03M7/30 , H03M9/00
摘要： Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.
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公开(公告)号：US11416323B2
公开(公告)日：2022-08-16
申请号：US16723855
申请日：2019-12-20
摘要： A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.
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