公开(公告)号：US20150016172A1

公开(公告)日：2015-01-15

申请号：US13941791

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Nuwan S. Jayasena ,  James M. O'Connor ,  Yasuko Eckert

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G06F3/0608 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0864 ,  G06F12/10 ,  G06F17/30477 ,  G06F17/30982 ,  G06F2212/60 ,  G11C5/02 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.

Abstract translation: 集成电路（IC）封装包括堆叠式存储器件。 堆叠式存储器件包括一组实现存储器单元电路的一个或多个堆叠存储器管芯。 堆叠裸片存储器件还包括电耦合到存储单元电路的一组或多个逻辑管芯。 一个或多个逻辑管芯的集合包括查询控制器和存储器控制器。 存储器控制器可耦合到堆叠式存储器件外部的至少一个器件。 查询控制器响应于从外部设备接收的查询命令，对存储在存储单元电路中的数据执行查询操作。

公开(公告)号：US20140181458A1

公开(公告)日：2014-06-26

申请号：US13726143

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  James M. O'Connor ,  Michael Ignatowski ,  Michael J. Schulte ,  Lisa R. Hsu ,  Nuwan S. Jayasena

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。

公开(公告)号：US20140156975A1

公开(公告)日：2014-06-05

申请号：US13690841

申请日：2012-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vilas SRIDHARAN ,  James M. O'Connor ,  Steven K. Reinhardt ,  Nuwan S. Jayasena ,  Michael J. Schulte ,  Dean A. Liberty

IPC: G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/3851 ,  G06F9/3887 ,  G06F11/1641 ,  G06F11/1691 ,  G06F11/1695

Abstract: In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match.

Abstract translation: 在一些实施例中，提供了一种用于提高处理器中的可靠性的方法。 该方法可以包括为处理器的第一和第二通道复制输入数据，第一和第二通道位于处理器的相同簇中，并且第一和第二通道各自产生与将要执行的指令相关联的相应值 并且响应于确定所生成的值不匹配，提供所生成的值不匹配的指示。